332 	/* Tlb flush all always is in bank0. */  in mtk_iommu_tlb_flush_all()
583 	/* Always use bank0 in sharing pgtable case */  in mtk_iommu_domain_finalise()
954 	const struct mtk_iommu_bank_data *bank0 = &data->bank[0];  in mtk_iommu_hw_init()  local
958 	 * Global control settings are in bank0. May re-init these global registers  in mtk_iommu_hw_init()
959 	 * since no sure if there is bank0 consumers.  in mtk_iommu_hw_init()
965 		regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);  in mtk_iommu_hw_init()
968 	writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);  in mtk_iommu_hw_init()
977 		writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);  in mtk_iommu_hw_init()
980 		writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS);  in mtk_iommu_hw_init()
982 		writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS);  in mtk_iommu_hw_init()
986 		regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);  in mtk_iommu_hw_init()
988 		writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);  in mtk_iommu_hw_init()
995 		regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);  in mtk_iommu_hw_init()
1001 	writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);  in mtk_iommu_hw_init()