Lines Matching +full:num +full:- +full:ss +full:- +full:bits
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
13 #include <linux/io-pgtable.h>
25 #include "msm_iommu_hw-8xxx.h"
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
73 if (iommu->clk) in __disable_clocks()
74 clk_disable(iommu->clk); in __disable_clocks()
75 clk_disable(iommu->pclk); in __disable_clocks()
124 list_for_each_entry(iommu, &priv->list_attached, dom_node) { in __flush_iotlb()
129 list_for_each_entry(master, &iommu->ctx_list, list) in __flush_iotlb()
130 SET_CTX_TLBIALL(iommu->base, master->num, 0); in __flush_iotlb()
147 list_for_each_entry(iommu, &priv->list_attached, dom_node) { in __flush_iotlb_range()
152 list_for_each_entry(master, &iommu->ctx_list, list) { in __flush_iotlb_range()
156 iova |= GET_CONTEXTIDR_ASID(iommu->base, in __flush_iotlb_range()
157 master->num); in __flush_iotlb_range()
158 SET_TLBIVA(iommu->base, master->num, iova); in __flush_iotlb_range()
160 } while (temp_size -= granule); in __flush_iotlb_range()
195 return -ENOSPC; in msm_iommu_alloc_ctx()
211 for (i = 0; i < master->num_mids; i++) { in config_mids()
212 mid = master->mids[i]; in config_mids()
213 ctx = master->num; in config_mids()
215 SET_M2VCBR_N(iommu->base, mid, 0); in config_mids()
216 SET_CBACR_N(iommu->base, ctx, 0); in config_mids()
219 SET_VMID(iommu->base, mid, 0); in config_mids()
222 SET_CBNDX(iommu->base, mid, ctx); in config_mids()
225 SET_CBVMID(iommu->base, ctx, 0); in config_mids()
228 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx); in config_mids()
230 /* Set security bit override to be Non-secure */ in config_mids()
231 SET_NSCFG(iommu->base, mid, 3); in config_mids()
273 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); in __program_context()
274 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); in __program_context()
278 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr); in __program_context()
279 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr); in __program_context()
316 INIT_LIST_HEAD(&priv->list_attached); in msm_iommu_domain_alloc()
318 priv->domain.geometry.aperture_start = 0; in msm_iommu_domain_alloc()
319 priv->domain.geometry.aperture_end = (1ULL << 32) - 1; in msm_iommu_domain_alloc()
320 priv->domain.geometry.force_aperture = true; in msm_iommu_domain_alloc()
322 return &priv->domain; in msm_iommu_domain_alloc()
342 spin_lock_init(&priv->pgtlock); in msm_iommu_domain_config()
344 priv->cfg = (struct io_pgtable_cfg) { in msm_iommu_domain_config()
349 .iommu_dev = priv->dev, in msm_iommu_domain_config()
352 priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv); in msm_iommu_domain_config()
353 if (!priv->iop) { in msm_iommu_domain_config()
354 dev_err(priv->dev, "Failed to allocate pgtable\n"); in msm_iommu_domain_config()
355 return -EINVAL; in msm_iommu_domain_config()
358 msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap; in msm_iommu_domain_config()
370 master = list_first_entry(&iommu->ctx_list, in find_iommu_for_dev()
373 if (master->of_node == dev->of_node) { in find_iommu_for_dev()
392 return ERR_PTR(-ENODEV); in msm_iommu_probe_device()
394 return &iommu->iommu; in msm_iommu_probe_device()
405 priv->dev = dev; in msm_iommu_attach_dev()
410 master = list_first_entry(&iommu->ctx_list, in msm_iommu_attach_dev()
413 if (master->of_node == dev->of_node) { in msm_iommu_attach_dev()
418 list_for_each_entry(master, &iommu->ctx_list, list) { in msm_iommu_attach_dev()
419 if (master->num) { in msm_iommu_attach_dev()
421 ret = -EEXIST; in msm_iommu_attach_dev()
424 master->num = in msm_iommu_attach_dev()
425 msm_iommu_alloc_ctx(iommu->context_map, in msm_iommu_attach_dev()
426 0, iommu->ncb); in msm_iommu_attach_dev()
427 if (IS_ERR_VALUE(master->num)) { in msm_iommu_attach_dev()
428 ret = -ENODEV; in msm_iommu_attach_dev()
432 __program_context(iommu->base, master->num, in msm_iommu_attach_dev()
436 list_add(&iommu->dom_node, &priv->list_attached); in msm_iommu_attach_dev()
455 free_io_pgtable_ops(priv->iop); in msm_iommu_detach_dev()
458 list_for_each_entry(iommu, &priv->list_attached, dom_node) { in msm_iommu_detach_dev()
463 list_for_each_entry(master, &iommu->ctx_list, list) { in msm_iommu_detach_dev()
464 msm_iommu_free_ctx(iommu->context_map, master->num); in msm_iommu_detach_dev()
465 __reset_context(iommu->base, master->num); in msm_iommu_detach_dev()
480 spin_lock_irqsave(&priv->pgtlock, flags); in msm_iommu_map()
481 ret = priv->iop->map(priv->iop, iova, pa, len, prot, GFP_ATOMIC); in msm_iommu_map()
482 spin_unlock_irqrestore(&priv->pgtlock, flags); in msm_iommu_map()
501 spin_lock_irqsave(&priv->pgtlock, flags); in msm_iommu_unmap()
502 len = priv->iop->unmap(priv->iop, iova, len, gather); in msm_iommu_unmap()
503 spin_unlock_irqrestore(&priv->pgtlock, flags); in msm_iommu_unmap()
521 iommu = list_first_entry(&priv->list_attached, in msm_iommu_iova_to_phys()
524 if (list_empty(&iommu->ctx_list)) in msm_iommu_iova_to_phys()
527 master = list_first_entry(&iommu->ctx_list, in msm_iommu_iova_to_phys()
537 SET_CTX_TLBIALL(iommu->base, master->num, 0); in msm_iommu_iova_to_phys()
538 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA); in msm_iommu_iova_to_phys()
540 par = GET_PAR(iommu->base, master->num); in msm_iommu_iova_to_phys()
543 if (GET_NOFAULT_SS(iommu->base, master->num)) in msm_iommu_iova_to_phys()
545 else /* Upper 20 bits from PAR, lower 12 from VA */ in msm_iommu_iova_to_phys()
548 if (GET_FAULT(iommu->base, master->num)) in msm_iommu_iova_to_phys()
571 (fsr & 0x40000000) ? "SS " : "", in print_ctx_regs()
589 if (list_empty(&(*iommu)->ctx_list)) { in insert_iommu_master()
593 return -ENOMEM; in insert_iommu_master()
595 master->of_node = dev->of_node; in insert_iommu_master()
596 list_add(&master->list, &(*iommu)->ctx_list); in insert_iommu_master()
600 for (sid = 0; sid < master->num_mids; sid++) in insert_iommu_master()
601 if (master->mids[sid] == spec->args[0]) { in insert_iommu_master()
607 master->mids[master->num_mids++] = spec->args[0]; in insert_iommu_master()
620 if (iter->dev->of_node == spec->np) { in qcom_iommu_of_xlate()
627 ret = -ENODEV; in qcom_iommu_of_xlate()
652 pr_err("base = %08x\n", (unsigned int)iommu->base); in msm_iommu_fault_handler()
658 for (i = 0; i < iommu->ncb; i++) { in msm_iommu_fault_handler()
659 fsr = GET_FSR(iommu->base, i); in msm_iommu_fault_handler()
663 print_ctx_regs(iommu->base, i); in msm_iommu_fault_handler()
664 SET_FSR(iommu->base, i, 0x4000000F); in msm_iommu_fault_handler()
704 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL); in msm_iommu_probe()
706 return -ENODEV; in msm_iommu_probe()
708 iommu->dev = &pdev->dev; in msm_iommu_probe()
709 INIT_LIST_HEAD(&iommu->ctx_list); in msm_iommu_probe()
711 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk"); in msm_iommu_probe()
712 if (IS_ERR(iommu->pclk)) in msm_iommu_probe()
713 return dev_err_probe(iommu->dev, PTR_ERR(iommu->pclk), in msm_iommu_probe()
716 ret = clk_prepare(iommu->pclk); in msm_iommu_probe()
718 return dev_err_probe(iommu->dev, ret, in msm_iommu_probe()
721 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk"); in msm_iommu_probe()
722 if (IS_ERR(iommu->clk)) { in msm_iommu_probe()
723 clk_unprepare(iommu->pclk); in msm_iommu_probe()
724 return dev_err_probe(iommu->dev, PTR_ERR(iommu->clk), in msm_iommu_probe()
728 ret = clk_prepare(iommu->clk); in msm_iommu_probe()
730 clk_unprepare(iommu->pclk); in msm_iommu_probe()
731 return dev_err_probe(iommu->dev, ret, "could not prepare iommu_clk\n"); in msm_iommu_probe()
735 iommu->base = devm_ioremap_resource(iommu->dev, r); in msm_iommu_probe()
736 if (IS_ERR(iommu->base)) { in msm_iommu_probe()
737 ret = dev_err_probe(iommu->dev, PTR_ERR(iommu->base), "could not get iommu base\n"); in msm_iommu_probe()
740 ioaddr = r->start; in msm_iommu_probe()
742 iommu->irq = platform_get_irq(pdev, 0); in msm_iommu_probe()
743 if (iommu->irq < 0) { in msm_iommu_probe()
744 ret = -ENODEV; in msm_iommu_probe()
748 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val); in msm_iommu_probe()
750 dev_err(iommu->dev, "could not get ncb\n"); in msm_iommu_probe()
753 iommu->ncb = val; in msm_iommu_probe()
755 msm_iommu_reset(iommu->base, iommu->ncb); in msm_iommu_probe()
756 SET_M(iommu->base, 0, 1); in msm_iommu_probe()
757 SET_PAR(iommu->base, 0, 0); in msm_iommu_probe()
758 SET_V2PCFG(iommu->base, 0, 1); in msm_iommu_probe()
759 SET_V2PPR(iommu->base, 0, 0); in msm_iommu_probe()
760 par = GET_PAR(iommu->base, 0); in msm_iommu_probe()
761 SET_V2PCFG(iommu->base, 0, 0); in msm_iommu_probe()
762 SET_M(iommu->base, 0, 0); in msm_iommu_probe()
766 ret = -ENODEV; in msm_iommu_probe()
770 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL, in msm_iommu_probe()
776 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret); in msm_iommu_probe()
780 list_add(&iommu->dev_node, &qcom_iommu_devices); in msm_iommu_probe()
782 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL, in msm_iommu_probe()
783 "msm-smmu.%pa", &ioaddr); in msm_iommu_probe()
785 pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr); in msm_iommu_probe()
789 ret = iommu_device_register(&iommu->iommu, &msm_iommu_ops, &pdev->dev); in msm_iommu_probe()
791 pr_err("Could not register msm-smmu at %pa\n", &ioaddr); in msm_iommu_probe()
796 iommu->base, iommu->irq, iommu->ncb); in msm_iommu_probe()
800 clk_unprepare(iommu->clk); in msm_iommu_probe()
801 clk_unprepare(iommu->pclk); in msm_iommu_probe()
806 { .compatible = "qcom,apq8064-iommu" },
814 clk_unprepare(iommu->clk); in msm_iommu_remove()
815 clk_unprepare(iommu->pclk); in msm_iommu_remove()