18 #include <linux/iommu.h>
54 static int __enable_clocks(struct msm_iommu_dev *iommu)  in __enable_clocks()  argument
58 	ret = clk_enable(iommu->pclk);  in __enable_clocks()
62 	if (iommu->clk) {  in __enable_clocks()
63 		ret = clk_enable(iommu->clk);  in __enable_clocks()
65 			clk_disable(iommu->pclk);  in __enable_clocks()
71 static void __disable_clocks(struct msm_iommu_dev *iommu)  in __disable_clocks()  argument
73 	if (iommu->clk)  in __disable_clocks()
74 		clk_disable(iommu->clk);  in __disable_clocks()
75 	clk_disable(iommu->pclk);  in __disable_clocks()
120 	struct msm_iommu_dev *iommu = NULL;  in __flush_iotlb()  local
124 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in __flush_iotlb()
125 		ret = __enable_clocks(iommu);  in __flush_iotlb()
129 		list_for_each_entry(master, &iommu->ctx_list, list)  in __flush_iotlb()
130 			SET_CTX_TLBIALL(iommu->base, master->num, 0);  in __flush_iotlb()
132 		__disable_clocks(iommu);  in __flush_iotlb()
142 	struct msm_iommu_dev *iommu = NULL;  in __flush_iotlb_range()  local
147 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in __flush_iotlb_range()
148 		ret = __enable_clocks(iommu);  in __flush_iotlb_range()
152 		list_for_each_entry(master, &iommu->ctx_list, list) {  in __flush_iotlb_range()
156 				iova |= GET_CONTEXTIDR_ASID(iommu->base,  in __flush_iotlb_range()
158 				SET_TLBIVA(iommu->base, master->num, iova);  in __flush_iotlb_range()
163 		__disable_clocks(iommu);  in __flush_iotlb_range()
206 static void config_mids(struct msm_iommu_dev *iommu,  in config_mids()  argument
215 		SET_M2VCBR_N(iommu->base, mid, 0);  in config_mids()
216 		SET_CBACR_N(iommu->base, ctx, 0);  in config_mids()
219 		SET_VMID(iommu->base, mid, 0);  in config_mids()
222 		SET_CBNDX(iommu->base, mid, ctx);  in config_mids()
225 		SET_CBVMID(iommu->base, ctx, 0);  in config_mids()
228 		SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);  in config_mids()
231 		SET_NSCFG(iommu->base, mid, 3);  in config_mids()
366 	struct msm_iommu_dev *iommu, *ret = NULL;  in find_iommu_for_dev()  local
369 	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {  in find_iommu_for_dev()
370 		master = list_first_entry(&iommu->ctx_list,  in find_iommu_for_dev()
374 			ret = iommu;  in find_iommu_for_dev()
384 	struct msm_iommu_dev *iommu;  in msm_iommu_probe_device()  local
388 	iommu = find_iommu_for_dev(dev);  in msm_iommu_probe_device()
391 	if (!iommu)  in msm_iommu_probe_device()
394 	return &iommu->iommu;  in msm_iommu_probe_device()
401 	struct msm_iommu_dev *iommu;  in msm_iommu_attach_dev()  local
409 	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {  in msm_iommu_attach_dev()
410 		master = list_first_entry(&iommu->ctx_list,  in msm_iommu_attach_dev()
414 			ret = __enable_clocks(iommu);  in msm_iommu_attach_dev()
418 			list_for_each_entry(master, &iommu->ctx_list, list) {  in msm_iommu_attach_dev()
425 					msm_iommu_alloc_ctx(iommu->context_map,  in msm_iommu_attach_dev()
426 							    0, iommu->ncb);  in msm_iommu_attach_dev()
431 				config_mids(iommu, master);  in msm_iommu_attach_dev()
432 				__program_context(iommu->base, master->num,  in msm_iommu_attach_dev()
435 			__disable_clocks(iommu);  in msm_iommu_attach_dev()
436 			list_add(&iommu->dom_node, &priv->list_attached);  in msm_iommu_attach_dev()
451 	struct msm_iommu_dev *iommu;  in msm_iommu_detach_dev()  local
458 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in msm_iommu_detach_dev()
459 		ret = __enable_clocks(iommu);  in msm_iommu_detach_dev()
463 		list_for_each_entry(master, &iommu->ctx_list, list) {  in msm_iommu_detach_dev()
464 			msm_iommu_free_ctx(iommu->context_map, master->num);  in msm_iommu_detach_dev()
465 			__reset_context(iommu->base, master->num);  in msm_iommu_detach_dev()
467 		__disable_clocks(iommu);  in msm_iommu_detach_dev()
512 	struct msm_iommu_dev *iommu;  in msm_iommu_iova_to_phys()  local
521 	iommu = list_first_entry(&priv->list_attached,  in msm_iommu_iova_to_phys()
524 	if (list_empty(&iommu->ctx_list))  in msm_iommu_iova_to_phys()
527 	master = list_first_entry(&iommu->ctx_list,  in msm_iommu_iova_to_phys()
532 	ret = __enable_clocks(iommu);  in msm_iommu_iova_to_phys()
537 	SET_CTX_TLBIALL(iommu->base, master->num, 0);  in msm_iommu_iova_to_phys()
538 	SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);  in msm_iommu_iova_to_phys()
540 	par = GET_PAR(iommu->base, master->num);  in msm_iommu_iova_to_phys()
543 	if (GET_NOFAULT_SS(iommu->base, master->num))  in msm_iommu_iova_to_phys()
548 	if (GET_FAULT(iommu->base, master->num))  in msm_iommu_iova_to_phys()
551 	__disable_clocks(iommu);  in msm_iommu_iova_to_phys()
583 				struct msm_iommu_dev **iommu,  in insert_iommu_master()  argument
589 	if (list_empty(&(*iommu)->ctx_list)) {  in insert_iommu_master()
596 		list_add(&master->list, &(*iommu)->ctx_list);  in insert_iommu_master()
614 	struct msm_iommu_dev *iommu = NULL, *iter;  in qcom_iommu_of_xlate()  local
621 			iommu = iter;  in qcom_iommu_of_xlate()
626 	if (!iommu) {  in qcom_iommu_of_xlate()
631 	ret = insert_iommu_master(dev, &iommu, spec);  in qcom_iommu_of_xlate()
640 	struct msm_iommu_dev *iommu = dev_id;  in msm_iommu_fault_handler()  local
646 	if (!iommu) {  in msm_iommu_fault_handler()
651 	pr_err("Unexpected IOMMU page fault!\n");  in msm_iommu_fault_handler()
652 	pr_err("base = %08x\n", (unsigned int)iommu->base);  in msm_iommu_fault_handler()
654 	ret = __enable_clocks(iommu);  in msm_iommu_fault_handler()
658 	for (i = 0; i < iommu->ncb; i++) {  in msm_iommu_fault_handler()
659 		fsr = GET_FSR(iommu->base, i);  in msm_iommu_fault_handler()
663 			print_ctx_regs(iommu->base, i);  in msm_iommu_fault_handler()
664 			SET_FSR(iommu->base, i, 0x4000000F);  in msm_iommu_fault_handler()
667 	__disable_clocks(iommu);  in msm_iommu_fault_handler()
687 		 * taken care when the iommu client does a writel before
701 	struct msm_iommu_dev *iommu;  in msm_iommu_probe()  local
704 	iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);  in msm_iommu_probe()
705 	if (!iommu)  in msm_iommu_probe()
708 	iommu->dev = &pdev->dev;  in msm_iommu_probe()
709 	INIT_LIST_HEAD(&iommu->ctx_list);  in msm_iommu_probe()
711 	iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");  in msm_iommu_probe()
712 	if (IS_ERR(iommu->pclk))  in msm_iommu_probe()
713 		return dev_err_probe(iommu->dev, PTR_ERR(iommu->pclk),  in msm_iommu_probe()
716 	ret = clk_prepare(iommu->pclk);  in msm_iommu_probe()
718 		return dev_err_probe(iommu->dev, ret,  in msm_iommu_probe()
721 	iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");  in msm_iommu_probe()
722 	if (IS_ERR(iommu->clk)) {  in msm_iommu_probe()
723 		clk_unprepare(iommu->pclk);  in msm_iommu_probe()
724 		return dev_err_probe(iommu->dev, PTR_ERR(iommu->clk),  in msm_iommu_probe()
728 	ret = clk_prepare(iommu->clk);  in msm_iommu_probe()
730 		clk_unprepare(iommu->pclk);  in msm_iommu_probe()
731 		return dev_err_probe(iommu->dev, ret, "could not prepare iommu_clk\n");  in msm_iommu_probe()
735 	iommu->base = devm_ioremap_resource(iommu->dev, r);  in msm_iommu_probe()
736 	if (IS_ERR(iommu->base)) {  in msm_iommu_probe()
737 		ret = dev_err_probe(iommu->dev, PTR_ERR(iommu->base), "could not get iommu base\n");  in msm_iommu_probe()
742 	iommu->irq = platform_get_irq(pdev, 0);  in msm_iommu_probe()
743 	if (iommu->irq < 0) {  in msm_iommu_probe()
748 	ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);  in msm_iommu_probe()
750 		dev_err(iommu->dev, "could not get ncb\n");  in msm_iommu_probe()
753 	iommu->ncb = val;  in msm_iommu_probe()
755 	msm_iommu_reset(iommu->base, iommu->ncb);  in msm_iommu_probe()
756 	SET_M(iommu->base, 0, 1);  in msm_iommu_probe()
757 	SET_PAR(iommu->base, 0, 0);  in msm_iommu_probe()
758 	SET_V2PCFG(iommu->base, 0, 1);  in msm_iommu_probe()
759 	SET_V2PPR(iommu->base, 0, 0);  in msm_iommu_probe()
760 	par = GET_PAR(iommu->base, 0);  in msm_iommu_probe()
761 	SET_V2PCFG(iommu->base, 0, 0);  in msm_iommu_probe()
762 	SET_M(iommu->base, 0, 0);  in msm_iommu_probe()
770 	ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,  in msm_iommu_probe()
774 					iommu);  in msm_iommu_probe()
776 		pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);  in msm_iommu_probe()
780 	list_add(&iommu->dev_node, &qcom_iommu_devices);  in msm_iommu_probe()
782 	ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,  in msm_iommu_probe()
789 	ret = iommu_device_register(&iommu->iommu, &msm_iommu_ops, &pdev->dev);  in msm_iommu_probe()
796 		iommu->base, iommu->irq, iommu->ncb);  in msm_iommu_probe()
800 	clk_unprepare(iommu->clk);  in msm_iommu_probe()
801 	clk_unprepare(iommu->pclk);  in msm_iommu_probe()
806 	{ .compatible = "qcom,apq8064-iommu" },
812 	struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);  in msm_iommu_remove()  local
814 	clk_unprepare(iommu->clk);  in msm_iommu_remove()
815 	clk_unprepare(iommu->pclk);  in msm_iommu_remove()