Lines Matching defs:intel_iommu

564 struct intel_iommu {  struct
565 	void __iomem	*reg; /* Pointer to hardware regs, virtual addr */
566 	u64 		reg_phys; /* physical address of hw register set */
567 	u64		reg_size; /* size of hw register set */
568 	u64		cap;
569 	u64		ecap;
570 	u64		vccap;
571 	u32		gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
572 	raw_spinlock_t	register_lock; /* protect register handling */
573 	int		seq_id;	/* sequence id of the iommu */
574 	int		agaw; /* agaw of this iommu */
575 	int		msagaw; /* max sagaw of this iommu */
576 	unsigned int 	irq, pr_irq;
577 	u16		segment;     /* PCI segment# */
578 	unsigned char 	name[13];    /* Device Name */
581 	unsigned long 	*domain_ids; /* bitmap of domains */
582 	unsigned long	*copied_tables; /* bitmap of copied tables */
583 	spinlock_t	lock; /* protect context, domain ids */
584 	struct root_entry *root_entry; /* virtual address */
586 	struct iommu_flush flush;
589 	struct page_req_dsc *prq;
590 	unsigned char prq_name[16];    /* Name for PRQ interrupt */
591 	unsigned long prq_seq_number;
592 	struct completion prq_complete;
593 	struct ioasid_allocator_ops pasid_allocator; /* Custom allocator for PASIDs */
595 	struct iopf_queue *iopf_queue;
596 	unsigned char iopfq_name[16];
597 	struct q_inval  *qi;            /* Queued invalidation info */
598 	u32 *iommu_state; /* Store iommu states between suspend and resume.*/
601 	struct ir_table *ir_table;	/* Interrupt remapping info */
602 	struct irq_domain *ir_domain;
603 	struct irq_domain *ir_msi_domain;
605 	struct iommu_device iommu;  /* IOMMU core code handle */
629 	struct intel_iommu *iommu; /* IOMMU used by this device */  argument