Lines Matching +full:segment +full:- +full:no +full:- +full:remap
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2006-2008 Intel Corporation
14 * These routines are used by both DMA-remapping and Interrupt-remapping
48 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
50 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
74 if (drhd->include_all) in dmar_register_drhd_unit()
75 list_add_tail_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
77 list_add_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
87 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE || in dmar_alloc_dev_scope()
88 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || in dmar_alloc_dev_scope()
89 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) in dmar_alloc_dev_scope()
91 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC && in dmar_alloc_dev_scope()
92 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) { in dmar_alloc_dev_scope()
95 start += scope->length; in dmar_alloc_dev_scope()
129 BUG_ON(dev->is_virtfn); in dmar_alloc_pci_notify_info()
135 if (pci_domain_nr(dev->bus) > U16_MAX) in dmar_alloc_pci_notify_info()
140 for (tmp = dev; tmp; tmp = tmp->bus->self) in dmar_alloc_pci_notify_info()
150 dmar_dev_scope_status = -ENOMEM; in dmar_alloc_pci_notify_info()
155 info->event = event; in dmar_alloc_pci_notify_info()
156 info->dev = dev; in dmar_alloc_pci_notify_info()
157 info->seg = pci_domain_nr(dev->bus); in dmar_alloc_pci_notify_info()
158 info->level = level; in dmar_alloc_pci_notify_info()
160 for (tmp = dev; tmp; tmp = tmp->bus->self) { in dmar_alloc_pci_notify_info()
161 level--; in dmar_alloc_pci_notify_info()
162 info->path[level].bus = tmp->bus->number; in dmar_alloc_pci_notify_info()
163 info->path[level].device = PCI_SLOT(tmp->devfn); in dmar_alloc_pci_notify_info()
164 info->path[level].function = PCI_FUNC(tmp->devfn); in dmar_alloc_pci_notify_info()
165 if (pci_is_root_bus(tmp->bus)) in dmar_alloc_pci_notify_info()
166 info->bus = tmp->bus->number; in dmar_alloc_pci_notify_info()
184 if (info->bus != bus) in dmar_match_pci_path()
186 if (info->level != count) in dmar_match_pci_path()
190 if (path[i].device != info->path[i].device || in dmar_match_pci_path()
191 path[i].function != info->path[i].function) in dmar_match_pci_path()
202 i = info->level - 1; in dmar_match_pci_path()
203 if (bus == info->path[i].bus && in dmar_match_pci_path()
204 path[0].device == info->path[i].device && in dmar_match_pci_path()
205 path[0].function == info->path[i].function) { in dmar_match_pci_path()
206 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n", in dmar_match_pci_path()
214 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
216 void *start, void*end, u16 segment, in dmar_insert_dev_scope() argument
221 struct device *tmp, *dev = &info->dev->dev; in dmar_insert_dev_scope()
225 if (segment != info->seg) in dmar_insert_dev_scope()
228 for (; start < end; start += scope->length) { in dmar_insert_dev_scope()
230 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && in dmar_insert_dev_scope()
231 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE) in dmar_insert_dev_scope()
235 level = (scope->length - sizeof(*scope)) / sizeof(*path); in dmar_insert_dev_scope()
236 if (!dmar_match_pci_path(info, scope->bus, path, level)) in dmar_insert_dev_scope()
245 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch in dmar_insert_dev_scope()
248 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && in dmar_insert_dev_scope()
249 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) || in dmar_insert_dev_scope()
250 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE && in dmar_insert_dev_scope()
251 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in dmar_insert_dev_scope()
252 info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) { in dmar_insert_dev_scope()
254 pci_name(info->dev)); in dmar_insert_dev_scope()
255 return -EINVAL; in dmar_insert_dev_scope()
260 devices[i].bus = info->dev->bus->number; in dmar_insert_dev_scope()
261 devices[i].devfn = info->dev->devfn; in dmar_insert_dev_scope()
272 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment, in dmar_remove_dev_scope() argument
278 if (info->seg != segment) in dmar_remove_dev_scope()
282 if (tmp == &info->dev->dev) { in dmar_remove_dev_scope()
299 if (dmaru->include_all) in dmar_pci_bus_add_dev()
302 drhd = container_of(dmaru->hdr, in dmar_pci_bus_add_dev()
305 ((void *)drhd) + drhd->header.length, in dmar_pci_bus_add_dev()
306 dmaru->segment, in dmar_pci_bus_add_dev()
307 dmaru->devices, dmaru->devices_cnt); in dmar_pci_bus_add_dev()
327 if (dmar_remove_dev_scope(info, dmaru->segment, in dmar_pci_bus_del_dev()
328 dmaru->devices, dmaru->devices_cnt)) in dmar_pci_bus_del_dev()
337 dev_set_msi_domain(&pdev->dev, dev_get_msi_domain(&physfn->dev)); in vf_inherit_msi_domain()
349 if (pdev->is_virtfn) { in dmar_pci_bus_notifier()
395 if (dmaru->segment == drhd->segment && in dmar_find_dmaru()
396 dmaru->reg_base_addr == drhd->address) in dmar_find_dmaru()
403 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
418 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL); in dmar_parse_one_drhd()
420 return -ENOMEM; in dmar_parse_one_drhd()
426 dmaru->hdr = (void *)(dmaru + 1); in dmar_parse_one_drhd()
427 memcpy(dmaru->hdr, header, header->length); in dmar_parse_one_drhd()
428 dmaru->reg_base_addr = drhd->address; in dmar_parse_one_drhd()
429 dmaru->segment = drhd->segment; in dmar_parse_one_drhd()
430 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ in dmar_parse_one_drhd()
431 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1), in dmar_parse_one_drhd()
432 ((void *)drhd) + drhd->header.length, in dmar_parse_one_drhd()
433 &dmaru->devices_cnt); in dmar_parse_one_drhd()
434 if (dmaru->devices_cnt && dmaru->devices == NULL) { in dmar_parse_one_drhd()
436 return -ENOMEM; in dmar_parse_one_drhd()
441 dmar_free_dev_scope(&dmaru->devices, in dmar_parse_one_drhd()
442 &dmaru->devices_cnt); in dmar_parse_one_drhd()
457 if (dmaru->devices && dmaru->devices_cnt) in dmar_free_drhd()
458 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt); in dmar_free_drhd()
459 if (dmaru->iommu) in dmar_free_drhd()
460 free_iommu(dmaru->iommu); in dmar_free_drhd()
470 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) { in dmar_parse_one_andd()
472 "Your BIOS is broken; ANDD object name is not NUL-terminated\n" in dmar_parse_one_andd()
478 return -EINVAL; in dmar_parse_one_andd()
480 pr_info("ANDD device: %x name: %s\n", andd->device_number, in dmar_parse_one_andd()
481 andd->device_name); in dmar_parse_one_andd()
494 if (drhd->reg_base_addr == rhsa->base_address) { in dmar_parse_one_rhsa()
495 int node = pxm_to_node(rhsa->proximity_domain); in dmar_parse_one_rhsa()
499 drhd->iommu->node = node; in dmar_parse_one_rhsa()
504 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" in dmar_parse_one_rhsa()
506 rhsa->base_address, in dmar_parse_one_rhsa()
527 switch (header->type) { in dmar_table_print_dmar_entry()
532 (unsigned long long)drhd->address, drhd->flags); in dmar_table_print_dmar_entry()
538 (unsigned long long)rmrr->base_address, in dmar_table_print_dmar_entry()
539 (unsigned long long)rmrr->end_address); in dmar_table_print_dmar_entry()
543 pr_info("ATSR flags: %#x\n", atsr->flags); in dmar_table_print_dmar_entry()
548 (unsigned long long)rhsa->base_address, in dmar_table_print_dmar_entry()
549 rhsa->proximity_domain); in dmar_table_print_dmar_entry()
552 /* We don't print this here because we need to sanity-check in dmar_table_print_dmar_entry()
557 pr_info("SATC flags: 0x%x\n", satc->flags); in dmar_table_print_dmar_entry()
563 * dmar_table_detect - checks to see if the platform supports DMAR devices
577 return ACPI_SUCCESS(status) ? 0 : -ENOENT; in dmar_table_detect()
587 next = (void *)iter + iter->length; in dmar_walk_remapping_entries()
588 if (iter->length == 0) { in dmar_walk_remapping_entries()
590 pr_debug(FW_BUG "Invalid 0-length structure\n"); in dmar_walk_remapping_entries()
595 return -EINVAL; in dmar_walk_remapping_entries()
598 if (cb->print_entry) in dmar_walk_remapping_entries()
601 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) { in dmar_walk_remapping_entries()
604 iter->type); in dmar_walk_remapping_entries()
605 } else if (cb->cb[iter->type]) { in dmar_walk_remapping_entries()
608 ret = cb->cb[iter->type](iter, cb->arg[iter->type]); in dmar_walk_remapping_entries()
611 } else if (!cb->ignore_unhandled) { in dmar_walk_remapping_entries()
612 pr_warn("No handler for DMAR structure type %d\n", in dmar_walk_remapping_entries()
613 iter->type); in dmar_walk_remapping_entries()
614 return -EINVAL; in dmar_walk_remapping_entries()
625 dmar->header.length - sizeof(*dmar), cb); in dmar_walk_dmar_table()
629 * parse_dmar_table - parses the DMA reporting table
663 return -ENODEV; in parse_dmar_table()
665 if (dmar->width < PAGE_SHIFT - 1) { in parse_dmar_table()
667 return -EINVAL; in parse_dmar_table()
670 pr_info("Host address width %d\n", dmar->width + 1); in parse_dmar_table()
673 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n"); in parse_dmar_table()
690 dev = dev->bus->self; in dmar_pci_device_match()
706 drhd = container_of(dmaru->hdr, in dmar_find_matched_drhd_unit()
710 if (dmaru->include_all && in dmar_find_matched_drhd_unit()
711 drhd->segment == pci_domain_nr(dev->bus)) in dmar_find_matched_drhd_unit()
714 if (dmar_pci_device_match(dmaru->devices, in dmar_find_matched_drhd_unit()
715 dmaru->devices_cnt, dev)) in dmar_find_matched_drhd_unit()
736 drhd = container_of(dmaru->hdr, in dmar_acpi_insert_dev_scope()
741 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length; in dmar_acpi_insert_dev_scope()
742 scope = ((void *)scope) + scope->length) { in dmar_acpi_insert_dev_scope()
743 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) in dmar_acpi_insert_dev_scope()
745 if (scope->enumeration_id != device_number) in dmar_acpi_insert_dev_scope()
750 dev_name(&adev->dev), dmaru->reg_base_addr, in dmar_acpi_insert_dev_scope()
751 scope->bus, path->device, path->function); in dmar_acpi_insert_dev_scope()
752 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp) in dmar_acpi_insert_dev_scope()
754 dmaru->devices[i].bus = scope->bus; in dmar_acpi_insert_dev_scope()
755 dmaru->devices[i].devfn = PCI_DEVFN(path->device, in dmar_acpi_insert_dev_scope()
756 path->function); in dmar_acpi_insert_dev_scope()
757 rcu_assign_pointer(dmaru->devices[i].dev, in dmar_acpi_insert_dev_scope()
758 get_device(&adev->dev)); in dmar_acpi_insert_dev_scope()
761 BUG_ON(i >= dmaru->devices_cnt); in dmar_acpi_insert_dev_scope()
764 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
765 device_number, dev_name(&adev->dev)); in dmar_acpi_insert_dev_scope()
773 return -ENODEV; in dmar_acpi_dev_scope_init()
776 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length; in dmar_acpi_dev_scope_init()
777 andd = ((void *)andd) + andd->header.length) { in dmar_acpi_dev_scope_init()
778 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) { in dmar_acpi_dev_scope_init()
783 andd->device_name, in dmar_acpi_dev_scope_init()
786 andd->device_name); in dmar_acpi_dev_scope_init()
792 andd->device_name); in dmar_acpi_dev_scope_init()
795 dmar_acpi_insert_dev_scope(andd->device_number, adev); in dmar_acpi_dev_scope_init()
810 dmar_dev_scope_status = -ENODEV; in dmar_dev_scope_init()
817 if (dev->is_virtfn) in dmar_dev_scope_init()
849 if (ret != -ENODEV) in dmar_table_init()
852 pr_info("No DMAR devices found\n"); in dmar_table_init()
853 ret = -ENODEV; in dmar_table_init()
885 if (!drhd->address) { in dmar_validate_one_drhd()
887 return -EINVAL; in dmar_validate_one_drhd()
891 addr = ioremap(drhd->address, VTD_PAGE_SIZE); in dmar_validate_one_drhd()
893 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE); in dmar_validate_one_drhd()
895 pr_warn("Can't validate DRHD address: %llx\n", drhd->address); in dmar_validate_one_drhd()
896 return -EINVAL; in dmar_validate_one_drhd()
907 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) { in dmar_validate_one_drhd()
908 warn_invalid_dmar(drhd->address, " returns all ones"); in dmar_validate_one_drhd()
909 return -EINVAL; in dmar_validate_one_drhd()
952 iounmap(iommu->reg); in unmap_iommu()
953 release_mem_region(iommu->reg_phys, iommu->reg_size); in unmap_iommu()
968 iommu->reg_phys = phys_addr; in map_iommu()
969 iommu->reg_size = VTD_PAGE_SIZE; in map_iommu()
971 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { in map_iommu()
973 err = -EBUSY; in map_iommu()
977 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
978 if (!iommu->reg) { in map_iommu()
980 err = -ENOMEM; in map_iommu()
984 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); in map_iommu()
985 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); in map_iommu()
987 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { in map_iommu()
988 err = -EINVAL; in map_iommu()
992 if (ecap_vcs(iommu->ecap)) in map_iommu()
993 iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG); in map_iommu()
996 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), in map_iommu()
997 cap_max_fault_reg_offset(iommu->cap)); in map_iommu()
999 if (map_size > iommu->reg_size) { in map_iommu()
1000 iounmap(iommu->reg); in map_iommu()
1001 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1002 iommu->reg_size = map_size; in map_iommu()
1003 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, in map_iommu()
1004 iommu->name)) { in map_iommu()
1006 err = -EBUSY; in map_iommu()
1009 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
1010 if (!iommu->reg) { in map_iommu()
1012 err = -ENOMEM; in map_iommu()
1020 iounmap(iommu->reg); in map_iommu()
1022 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1031 int agaw = -1; in alloc_iommu()
1032 int msagaw = -1; in alloc_iommu()
1035 if (!drhd->reg_base_addr) { in alloc_iommu()
1037 return -EINVAL; in alloc_iommu()
1042 return -ENOMEM; in alloc_iommu()
1044 iommu->seq_id = ida_alloc_range(&dmar_seq_ids, 0, in alloc_iommu()
1045 DMAR_UNITS_SUPPORTED - 1, GFP_KERNEL); in alloc_iommu()
1046 if (iommu->seq_id < 0) { in alloc_iommu()
1048 err = iommu->seq_id; in alloc_iommu()
1051 sprintf(iommu->name, "dmar%d", iommu->seq_id); in alloc_iommu()
1053 err = map_iommu(iommu, drhd->reg_base_addr); in alloc_iommu()
1055 pr_err("Failed to map %s\n", iommu->name); in alloc_iommu()
1059 err = -EINVAL; in alloc_iommu()
1060 if (cap_sagaw(iommu->cap) == 0) { in alloc_iommu()
1061 pr_info("%s: No supported address widths. Not attempting DMA translation.\n", in alloc_iommu()
1062 iommu->name); in alloc_iommu()
1063 drhd->ignored = 1; in alloc_iommu()
1066 if (!drhd->ignored) { in alloc_iommu()
1070 iommu->seq_id); in alloc_iommu()
1071 drhd->ignored = 1; in alloc_iommu()
1074 if (!drhd->ignored) { in alloc_iommu()
1078 iommu->seq_id); in alloc_iommu()
1079 drhd->ignored = 1; in alloc_iommu()
1080 agaw = -1; in alloc_iommu()
1083 iommu->agaw = agaw; in alloc_iommu()
1084 iommu->msagaw = msagaw; in alloc_iommu()
1085 iommu->segment = drhd->segment; in alloc_iommu()
1087 iommu->node = NUMA_NO_NODE; in alloc_iommu()
1089 ver = readl(iommu->reg + DMAR_VER_REG); in alloc_iommu()
1091 iommu->name, in alloc_iommu()
1092 (unsigned long long)drhd->reg_base_addr, in alloc_iommu()
1094 (unsigned long long)iommu->cap, in alloc_iommu()
1095 (unsigned long long)iommu->ecap); in alloc_iommu()
1098 sts = readl(iommu->reg + DMAR_GSTS_REG); in alloc_iommu()
1100 iommu->gcmd |= DMA_GCMD_IRE; in alloc_iommu()
1102 iommu->gcmd |= DMA_GCMD_TE; in alloc_iommu()
1104 iommu->gcmd |= DMA_GCMD_QIE; in alloc_iommu()
1106 raw_spin_lock_init(&iommu->register_lock); in alloc_iommu()
1113 if (intel_iommu_enabled && !drhd->ignored) { in alloc_iommu()
1114 err = iommu_device_sysfs_add(&iommu->iommu, NULL, in alloc_iommu()
1116 "%s", iommu->name); in alloc_iommu()
1120 err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL); in alloc_iommu()
1125 drhd->iommu = iommu; in alloc_iommu()
1126 iommu->drhd = drhd; in alloc_iommu()
1131 iommu_device_sysfs_remove(&iommu->iommu); in alloc_iommu()
1135 ida_free(&dmar_seq_ids, iommu->seq_id); in alloc_iommu()
1143 if (intel_iommu_enabled && !iommu->drhd->ignored) { in free_iommu()
1144 iommu_device_unregister(&iommu->iommu); in free_iommu()
1145 iommu_device_sysfs_remove(&iommu->iommu); in free_iommu()
1148 if (iommu->irq) { in free_iommu()
1149 if (iommu->pr_irq) { in free_iommu()
1150 free_irq(iommu->pr_irq, iommu); in free_iommu()
1151 dmar_free_hwirq(iommu->pr_irq); in free_iommu()
1152 iommu->pr_irq = 0; in free_iommu()
1154 free_irq(iommu->irq, iommu); in free_iommu()
1155 dmar_free_hwirq(iommu->irq); in free_iommu()
1156 iommu->irq = 0; in free_iommu()
1159 if (iommu->qi) { in free_iommu()
1160 free_page((unsigned long)iommu->qi->desc); in free_iommu()
1161 kfree(iommu->qi->desc_status); in free_iommu()
1162 kfree(iommu->qi); in free_iommu()
1165 if (iommu->reg) in free_iommu()
1168 ida_free(&dmar_seq_ids, iommu->seq_id); in free_iommu()
1177 while (qi->desc_status[qi->free_tail] == QI_DONE || in reclaim_free_desc()
1178 qi->desc_status[qi->free_tail] == QI_ABORT) { in reclaim_free_desc()
1179 qi->desc_status[qi->free_tail] = QI_FREE; in reclaim_free_desc()
1180 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; in reclaim_free_desc()
1181 qi->free_cnt++; in reclaim_free_desc()
1189 return "Context-cache Invalidation"; in qi_type_string()
1193 return "Device-TLB Invalidation"; in qi_type_string()
1199 return "PASID-based IOTLB Invalidation"; in qi_type_string()
1201 return "PASID-cache Invalidation"; in qi_type_string()
1203 return "PASID-based Device-TLB Invalidation"; in qi_type_string()
1213 unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG); in qi_dump_fault()
1214 u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG); in qi_dump_fault()
1215 struct qi_desc *desc = iommu->qi->desc + head; in qi_dump_fault()
1218 pr_err("VT-d detected Invalidation Queue Error: Reason %llx", in qi_dump_fault()
1221 pr_err("VT-d detected Invalidation Time-out Error: SID %llx", in qi_dump_fault()
1224 pr_err("VT-d detected Invalidation Completion Error: SID %llx", in qi_dump_fault()
1228 qi_type_string(desc->qw0 & 0xf), in qi_dump_fault()
1229 (unsigned long long)desc->qw0, in qi_dump_fault()
1230 (unsigned long long)desc->qw1); in qi_dump_fault()
1232 head = ((head >> qi_shift(iommu)) + QI_LENGTH - 1) % QI_LENGTH; in qi_dump_fault()
1234 desc = iommu->qi->desc + head; in qi_dump_fault()
1237 qi_type_string(desc->qw0 & 0xf), in qi_dump_fault()
1238 (unsigned long long)desc->qw0, in qi_dump_fault()
1239 (unsigned long long)desc->qw1); in qi_dump_fault()
1246 struct q_inval *qi = iommu->qi; in qi_check_fault()
1249 if (qi->desc_status[wait_index] == QI_ABORT) in qi_check_fault()
1250 return -EAGAIN; in qi_check_fault()
1252 fault = readl(iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1258 * with the error. No new descriptors are fetched until the IQE in qi_check_fault()
1262 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1264 struct qi_desc *desc = qi->desc + head; in qi_check_fault()
1267 * desc->qw2 and desc->qw3 are either reserved or in qi_check_fault()
1271 memcpy(desc, qi->desc + (wait_index << shift), in qi_check_fault()
1273 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1275 return -EINVAL; in qi_check_fault()
1281 * No new descriptors are fetched until the ITE is cleared. in qi_check_fault()
1284 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1285 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1287 tail = readl(iommu->reg + DMAR_IQT_REG); in qi_check_fault()
1288 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1290 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1291 pr_info("Invalidation Time-out Error (ITE) cleared\n"); in qi_check_fault()
1294 if (qi->desc_status[head] == QI_IN_USE) in qi_check_fault()
1295 qi->desc_status[head] = QI_ABORT; in qi_check_fault()
1296 head = (head - 2 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1299 if (qi->desc_status[wait_index] == QI_ABORT) in qi_check_fault()
1300 return -EAGAIN; in qi_check_fault()
1304 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1321 struct q_inval *qi = iommu->qi; in qi_submit_sync()
1335 type = desc->qw0 & GENMASK_ULL(3, 0); in qi_submit_sync()
1352 raw_spin_lock_irqsave(&qi->q_lock, flags); in qi_submit_sync()
1358 while (qi->free_cnt < count + 2) { in qi_submit_sync()
1359 raw_spin_unlock_irqrestore(&qi->q_lock, flags); in qi_submit_sync()
1361 raw_spin_lock_irqsave(&qi->q_lock, flags); in qi_submit_sync()
1364 index = qi->free_head; in qi_submit_sync()
1370 memcpy(qi->desc + offset, &desc[i], 1 << shift); in qi_submit_sync()
1371 qi->desc_status[(index + i) % QI_LENGTH] = QI_IN_USE; in qi_submit_sync()
1375 qi->desc_status[wait_index] = QI_IN_USE; in qi_submit_sync()
1381 wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]); in qi_submit_sync()
1386 memcpy(qi->desc + offset, &wait_desc, 1 << shift); in qi_submit_sync()
1388 qi->free_head = (qi->free_head + count + 1) % QI_LENGTH; in qi_submit_sync()
1389 qi->free_cnt -= count + 1; in qi_submit_sync()
1395 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); in qi_submit_sync()
1397 while (qi->desc_status[wait_index] != QI_DONE) { in qi_submit_sync()
1409 raw_spin_unlock(&qi->q_lock); in qi_submit_sync()
1411 raw_spin_lock(&qi->q_lock); in qi_submit_sync()
1415 qi->desc_status[(index + i) % QI_LENGTH] = QI_DONE; in qi_submit_sync()
1418 raw_spin_unlock_irqrestore(&qi->q_lock, flags); in qi_submit_sync()
1420 if (rc == -EAGAIN) in qi_submit_sync()
1425 ktime_to_ns(ktime_get()) - iotlb_start_ktime); in qi_submit_sync()
1429 ktime_to_ns(ktime_get()) - devtlb_start_ktime); in qi_submit_sync()
1433 ktime_to_ns(ktime_get()) - iec_start_ktime); in qi_submit_sync()
1476 if (cap_write_drain(iommu->cap)) in qi_flush_iotlb()
1479 if (cap_read_drain(iommu->cap)) in qi_flush_iotlb()
1498 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; in qi_flush_dev_iotlb()
1514 /* PASID-based IOTLB invalidation */
1521 * npages == -1 means a PASID-selective invalidation, otherwise, in qi_flush_piotlb()
1522 * a positive value for Page-selective-within-PASID invalidation. in qi_flush_piotlb()
1530 if (npages == -1) { in qi_flush_piotlb()
1555 /* PASID-based device IOTLB Invalidate */
1559 unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1); in qi_flush_dev_iotlb_pasid()
1569 * range. VT-d spec 6.5.2.6. in qi_flush_dev_iotlb_pasid()
1576 pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n", in qi_flush_dev_iotlb_pasid()
1588 desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1, in qi_flush_dev_iotlb_pasid()
1618 if (!ecap_qis(iommu->ecap)) in dmar_disable_qi()
1621 raw_spin_lock_irqsave(&iommu->register_lock, flags); in dmar_disable_qi()
1623 sts = readl(iommu->reg + DMAR_GSTS_REG); in dmar_disable_qi()
1630 while ((readl(iommu->reg + DMAR_IQT_REG) != in dmar_disable_qi()
1631 readl(iommu->reg + DMAR_IQH_REG)) && in dmar_disable_qi()
1632 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) in dmar_disable_qi()
1635 iommu->gcmd &= ~DMA_GCMD_QIE; in dmar_disable_qi()
1636 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in dmar_disable_qi()
1641 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in dmar_disable_qi()
1651 struct q_inval *qi = iommu->qi; in __dmar_enable_qi()
1652 u64 val = virt_to_phys(qi->desc); in __dmar_enable_qi()
1654 qi->free_head = qi->free_tail = 0; in __dmar_enable_qi()
1655 qi->free_cnt = QI_LENGTH; in __dmar_enable_qi()
1661 if (ecap_smts(iommu->ecap)) in __dmar_enable_qi()
1664 raw_spin_lock_irqsave(&iommu->register_lock, flags); in __dmar_enable_qi()
1667 writel(0, iommu->reg + DMAR_IQT_REG); in __dmar_enable_qi()
1669 dmar_writeq(iommu->reg + DMAR_IQA_REG, val); in __dmar_enable_qi()
1671 iommu->gcmd |= DMA_GCMD_QIE; in __dmar_enable_qi()
1672 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in __dmar_enable_qi()
1677 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in __dmar_enable_qi()
1682 * interrupt-remapping. Also used by DMA-remapping, which replaces
1690 if (!ecap_qis(iommu->ecap)) in dmar_enable_qi()
1691 return -ENOENT; in dmar_enable_qi()
1696 if (iommu->qi) in dmar_enable_qi()
1699 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); in dmar_enable_qi()
1700 if (!iommu->qi) in dmar_enable_qi()
1701 return -ENOMEM; in dmar_enable_qi()
1703 qi = iommu->qi; in dmar_enable_qi()
1709 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, in dmar_enable_qi()
1710 !!ecap_smts(iommu->ecap)); in dmar_enable_qi()
1713 iommu->qi = NULL; in dmar_enable_qi()
1714 return -ENOMEM; in dmar_enable_qi()
1717 qi->desc = page_address(desc_page); in dmar_enable_qi()
1719 qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC); in dmar_enable_qi()
1720 if (!qi->desc_status) { in dmar_enable_qi()
1721 free_page((unsigned long) qi->desc); in dmar_enable_qi()
1723 iommu->qi = NULL; in dmar_enable_qi()
1724 return -ENOMEM; in dmar_enable_qi()
1727 raw_spin_lock_init(&qi->q_lock); in dmar_enable_qi()
1734 /* iommu interrupt handling. Most stuff are MSI-like. */
1754 "non-zero reserved fields in RTP",
1755 "non-zero reserved fields in CTP",
1756 "non-zero reserved fields in PTE",
1764 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
1767 "SM: Non-zero reserved field set in Root Entry",
1768 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
1771 "SM: Non-zero reserved field set in the Context Entry",
1776 "SM: PRE field in Context-Entry is clear",
1777 "SM: RID_PASID field error in Context-Entry",
1778 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
1781 "SM: Non-zero reserved field set in PASID Directory Entry",
1782 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
1785 "SM: Non-zero reserved field set in PASID Table Entry",
1786 "SM: Invalid Scalable-Mode PASID Table Entry",
1789 "Unknown", "Unknown",/* 0x5E-0x5F */
1790 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x…
1791 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x…
1792 "SM: Error attempting to access first-level paging entry",
1793 "SM: Present bit in first-level paging entry is clear",
1794 "SM: Non-zero reserved field set in first-level paging entry",
1795 "SM: Error attempting to access FL-PML4 entry",
1796 "SM: First-level entry address beyond MGAW in Nested translation",
1797 "SM: Read permission error in FL-PML4 entry in Nested translation",
1798 "SM: Read permission error in first-level paging entry in Nested translation",
1799 "SM: Write permission error in first-level paging entry in Nested translation",
1800 "SM: Error attempting to access second-level paging entry",
1801 "SM: Read/Write permission error in second-level paging entry",
1802 "SM: Non-zero reserved field set in second-level paging entry",
1803 "SM: Invalid second-level page table pointer",
1804 "SM: A/D bit update needed in second-level entry when set up in no snoop",
1805 "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
1806 "SM: Address in first-level translation is not canonical",
1807 "SM: U/S set 0 for first-level translation with user privilege",
1808 "SM: No execute permission for request with PASID and ER=1",
1810 "SM: Second-level entry address beyond the max",
1811 "SM: No write permission for Write/AtomicOp request",
1812 "SM: No read permission for Read/AtomicOp request",
1813 "SM: Invalid address-interrupt address",
1814 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x…
1815 "SM: A/D bit update needed in first-level entry when set up in no snoop",
1820 "Detected reserved fields in the decoded interrupt-remapped request",
1821 "Interrupt index exceeded the interrupt-remapping table size",
1823 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1826 "Blocked an interrupt request due to source-id verification failure",
1831 if (fault_reason >= 0x20 && (fault_reason - 0x20 < in dmar_get_fault_reason()
1834 return irq_remap_fault_reasons[fault_reason - 0x20]; in dmar_get_fault_reason()
1835 } else if (fault_reason >= 0x30 && (fault_reason - 0x30 < in dmar_get_fault_reason()
1838 return dma_remap_sm_fault_reasons[fault_reason - 0x30]; in dmar_get_fault_reason()
1851 if (iommu->irq == irq) in dmar_msi_reg()
1853 else if (iommu->pr_irq == irq) in dmar_msi_reg()
1862 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_unmask()
1866 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_unmask()
1867 writel(0, iommu->reg + reg); in dmar_msi_unmask()
1869 readl(iommu->reg + reg); in dmar_msi_unmask()
1870 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_unmask()
1876 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_mask()
1880 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_mask()
1881 writel(DMA_FECTL_IM, iommu->reg + reg); in dmar_msi_mask()
1883 readl(iommu->reg + reg); in dmar_msi_mask()
1884 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_mask()
1893 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_write()
1894 writel(msg->data, iommu->reg + reg + 4); in dmar_msi_write()
1895 writel(msg->address_lo, iommu->reg + reg + 8); in dmar_msi_write()
1896 writel(msg->address_hi, iommu->reg + reg + 12); in dmar_msi_write()
1897 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_write()
1906 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_read()
1907 msg->data = readl(iommu->reg + reg + 4); in dmar_msi_read()
1908 msg->address_lo = readl(iommu->reg + reg + 8); in dmar_msi_read()
1909 msg->address_hi = readl(iommu->reg + reg + 12); in dmar_msi_read()
1910 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_read()
1923 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index 0x%llx [fault reason 0x%02x] %s\n", in dmar_fault_do_one()
1960 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
1961 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in dmar_fault()
1970 reg = cap_fault_reg_offset(iommu->cap); in dmar_fault()
1983 data = readl(iommu->reg + reg + in dmar_fault()
1993 data = readl(iommu->reg + reg + in dmar_fault()
1998 guest_addr = dmar_readq(iommu->reg + reg + in dmar_fault()
2004 writel(DMA_FRCD_F, iommu->reg + reg + in dmar_fault()
2007 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
2010 /* Using pasid -1 if pasid is not present */ in dmar_fault()
2016 if (fault_index >= cap_num_fault_regs(iommu->cap)) in dmar_fault()
2018 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
2022 iommu->reg + DMAR_FSTS_REG); in dmar_fault()
2025 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
2036 if (iommu->irq) in dmar_set_interrupt()
2039 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); in dmar_set_interrupt()
2041 iommu->irq = irq; in dmar_set_interrupt()
2043 pr_err("No free IRQ vectors\n"); in dmar_set_interrupt()
2044 return -EINVAL; in dmar_set_interrupt()
2047 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); in dmar_set_interrupt()
2067 (unsigned long long)drhd->reg_base_addr, ret); in enable_drhd_fault_handling()
2068 return -1; in enable_drhd_fault_handling()
2074 dmar_fault(iommu->irq, iommu); in enable_drhd_fault_handling()
2075 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
2076 writel(fault_status, iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
2083 * Re-enable Queued Invalidation interface.
2087 if (!ecap_qis(iommu->ecap)) in dmar_reenable_qi()
2088 return -ENOENT; in dmar_reenable_qi()
2090 if (!iommu->qi) in dmar_reenable_qi()
2091 return -ENOENT; in dmar_reenable_qi()
2098 * Then enable queued invalidation again. Since there is no pending in dmar_reenable_qi()
2099 * invalidation requests now, it's safe to re-enable queued in dmar_reenable_qi()
2116 return dmar->flags & 0x1; in dmar_ir_support()
2137 list_del(&dmaru->list); in dmar_free_unused_resources()
2150 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
2175 int ret = -ENODEV; in dmar_walk_dsm_resource()
2192 return -ENODEV; in dmar_walk_dsm_resource()
2197 start = (struct acpi_dmar_header *)obj->buffer.pointer; in dmar_walk_dsm_resource()
2198 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback); in dmar_walk_dsm_resource()
2212 return -ENODEV; in dmar_hp_add_drhd()
2234 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) { in dmar_hp_remove_drhd()
2235 for_each_active_dev_scope(dmaru->devices, in dmar_hp_remove_drhd()
2236 dmaru->devices_cnt, i, dev) in dmar_hp_remove_drhd()
2237 return -EBUSY; in dmar_hp_remove_drhd()
2253 list_del_rcu(&dmaru->list); in dmar_hp_release_drhd()
2274 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n"); in dmar_hotplug_insert()
2362 return -ENXIO; in dmar_device_hotplug()
2389 * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table
2393 * sure no device can issue DMA outside of RMRR regions.
2406 ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN); in dmar_platform_optin()