28 #include <linux/iommu.h>
33 #include "iommu.h"
66 static void free_iommu(struct intel_iommu *iommu);
459 	if (dmaru->iommu)  in dmar_free_drhd()
460 		free_iommu(dmaru->iommu);  in dmar_free_drhd()
499 			drhd->iommu->node = node;  in dmar_parse_one_rhsa()
764 	pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",  in dmar_acpi_insert_dev_scope()
937 		x86_init.iommu.iommu_init = intel_iommu_init;  in detect_intel_iommu()
950 static void unmap_iommu(struct intel_iommu *iommu)  in unmap_iommu()  argument
952 	iounmap(iommu->reg);  in unmap_iommu()
953 	release_mem_region(iommu->reg_phys, iommu->reg_size);  in unmap_iommu()
957  * map_iommu: map the iommu's registers
958  * @iommu: the iommu to map
961  * Memory map the iommu's registers.  Start w/ a single page, and
964 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)  in map_iommu()  argument
968 	iommu->reg_phys = phys_addr;  in map_iommu()
969 	iommu->reg_size = VTD_PAGE_SIZE;  in map_iommu()
971 	if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {  in map_iommu()
977 	iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);  in map_iommu()
978 	if (!iommu->reg) {  in map_iommu()
984 	iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);  in map_iommu()
985 	iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);  in map_iommu()
987 	if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {  in map_iommu()
992 	if (ecap_vcs(iommu->ecap))  in map_iommu()
993 		iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG);  in map_iommu()
996 	map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),  in map_iommu()
997 			 cap_max_fault_reg_offset(iommu->cap));  in map_iommu()
999 	if (map_size > iommu->reg_size) {  in map_iommu()
1000 		iounmap(iommu->reg);  in map_iommu()
1001 		release_mem_region(iommu->reg_phys, iommu->reg_size);  in map_iommu()
1002 		iommu->reg_size = map_size;  in map_iommu()
1003 		if (!request_mem_region(iommu->reg_phys, iommu->reg_size,  in map_iommu()
1004 					iommu->name)) {  in map_iommu()
1009 		iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);  in map_iommu()
1010 		if (!iommu->reg) {  in map_iommu()
1020 	iounmap(iommu->reg);  in map_iommu()
1022 	release_mem_region(iommu->reg_phys, iommu->reg_size);  in map_iommu()
1029 	struct intel_iommu *iommu;  in alloc_iommu()  local
1040 	iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);  in alloc_iommu()
1041 	if (!iommu)  in alloc_iommu()
1044 	iommu->seq_id = ida_alloc_range(&dmar_seq_ids, 0,  in alloc_iommu()
1046 	if (iommu->seq_id < 0) {  in alloc_iommu()
1048 		err = iommu->seq_id;  in alloc_iommu()
1051 	sprintf(iommu->name, "dmar%d", iommu->seq_id);  in alloc_iommu()
1053 	err = map_iommu(iommu, drhd->reg_base_addr);  in alloc_iommu()
1055 		pr_err("Failed to map %s\n", iommu->name);  in alloc_iommu()
1060 	if (cap_sagaw(iommu->cap) == 0) {  in alloc_iommu()
1062 			iommu->name);  in alloc_iommu()
1067 		agaw = iommu_calculate_agaw(iommu);  in alloc_iommu()
1069 			pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",  in alloc_iommu()
1070 			       iommu->seq_id);  in alloc_iommu()
1075 		msagaw = iommu_calculate_max_sagaw(iommu);  in alloc_iommu()
1077 			pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",  in alloc_iommu()
1078 			       iommu->seq_id);  in alloc_iommu()
1083 	iommu->agaw = agaw;  in alloc_iommu()
1084 	iommu->msagaw = msagaw;  in alloc_iommu()
1085 	iommu->segment = drhd->segment;  in alloc_iommu()
1087 	iommu->node = NUMA_NO_NODE;  in alloc_iommu()
1089 	ver = readl(iommu->reg + DMAR_VER_REG);  in alloc_iommu()
1091 		iommu->name,  in alloc_iommu()
1094 		(unsigned long long)iommu->cap,  in alloc_iommu()
1095 		(unsigned long long)iommu->ecap);  in alloc_iommu()
1098 	sts = readl(iommu->reg + DMAR_GSTS_REG);  in alloc_iommu()
1100 		iommu->gcmd |= DMA_GCMD_IRE;  in alloc_iommu()
1102 		iommu->gcmd |= DMA_GCMD_TE;  in alloc_iommu()
1104 		iommu->gcmd |= DMA_GCMD_QIE;  in alloc_iommu()
1106 	raw_spin_lock_init(&iommu->register_lock);  in alloc_iommu()
1114 		err = iommu_device_sysfs_add(&iommu->iommu, NULL,  in alloc_iommu()
1116 					     "%s", iommu->name);  in alloc_iommu()
1120 		err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL);  in alloc_iommu()
1125 	drhd->iommu = iommu;  in alloc_iommu()
1126 	iommu->drhd = drhd;  in alloc_iommu()
1131 	iommu_device_sysfs_remove(&iommu->iommu);  in alloc_iommu()
1133 	unmap_iommu(iommu);  in alloc_iommu()
1135 	ida_free(&dmar_seq_ids, iommu->seq_id);  in alloc_iommu()
1137 	kfree(iommu);  in alloc_iommu()
1141 static void free_iommu(struct intel_iommu *iommu)  in free_iommu()  argument
1143 	if (intel_iommu_enabled && !iommu->drhd->ignored) {  in free_iommu()
1144 		iommu_device_unregister(&iommu->iommu);  in free_iommu()
1145 		iommu_device_sysfs_remove(&iommu->iommu);  in free_iommu()
1148 	if (iommu->irq) {  in free_iommu()
1149 		if (iommu->pr_irq) {  in free_iommu()
1150 			free_irq(iommu->pr_irq, iommu);  in free_iommu()
1151 			dmar_free_hwirq(iommu->pr_irq);  in free_iommu()
1152 			iommu->pr_irq = 0;  in free_iommu()
1154 		free_irq(iommu->irq, iommu);  in free_iommu()
1155 		dmar_free_hwirq(iommu->irq);  in free_iommu()
1156 		iommu->irq = 0;  in free_iommu()
1159 	if (iommu->qi) {  in free_iommu()
1160 		free_page((unsigned long)iommu->qi->desc);  in free_iommu()
1161 		kfree(iommu->qi->desc_status);  in free_iommu()
1162 		kfree(iommu->qi);  in free_iommu()
1165 	if (iommu->reg)  in free_iommu()
1166 		unmap_iommu(iommu);  in free_iommu()
1168 	ida_free(&dmar_seq_ids, iommu->seq_id);  in free_iommu()
1169 	kfree(iommu);  in free_iommu()
1211 static void qi_dump_fault(struct intel_iommu *iommu, u32 fault)  in qi_dump_fault()  argument
1213 	unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG);  in qi_dump_fault()
1214 	u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG);  in qi_dump_fault()
1215 	struct qi_desc *desc = iommu->qi->desc + head;  in qi_dump_fault()
1232 	head = ((head >> qi_shift(iommu)) + QI_LENGTH - 1) % QI_LENGTH;  in qi_dump_fault()
1233 	head <<= qi_shift(iommu);  in qi_dump_fault()
1234 	desc = iommu->qi->desc + head;  in qi_dump_fault()
1242 static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index)  in qi_check_fault()  argument
1246 	struct q_inval *qi = iommu->qi;  in qi_check_fault()
1247 	int shift = qi_shift(iommu);  in qi_check_fault()
1252 	fault = readl(iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1254 		qi_dump_fault(iommu, fault);  in qi_check_fault()
1262 		head = readl(iommu->reg + DMAR_IQH_REG);  in qi_check_fault()
1273 			writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1284 		head = readl(iommu->reg + DMAR_IQH_REG);  in qi_check_fault()
1287 		tail = readl(iommu->reg + DMAR_IQT_REG);  in qi_check_fault()
1290 		writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1304 		writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1318 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc,  in qi_submit_sync()  argument
1321 	struct q_inval *qi = iommu->qi;  in qi_submit_sync()
1338 	    dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IOTLB))  in qi_submit_sync()
1342 	    dmar_latency_enabled(iommu, DMAR_LATENCY_INV_DEVTLB))  in qi_submit_sync()
1346 	    dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IEC))  in qi_submit_sync()
1366 	shift = qi_shift(iommu);  in qi_submit_sync()
1372 		trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1,  in qi_submit_sync()
1395 	writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG);  in qi_submit_sync()
1405 		rc = qi_check_fault(iommu, index, wait_index);  in qi_submit_sync()
1424 		dmar_latency_update(iommu, DMAR_LATENCY_INV_IOTLB,  in qi_submit_sync()
1428 		dmar_latency_update(iommu, DMAR_LATENCY_INV_DEVTLB,  in qi_submit_sync()
1432 		dmar_latency_update(iommu, DMAR_LATENCY_INV_IEC,  in qi_submit_sync()
1441 void qi_global_iec(struct intel_iommu *iommu)  in qi_global_iec()  argument
1451 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_global_iec()
1454 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,  in qi_flush_context()  argument
1465 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_context()
1468 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,  in qi_flush_iotlb()  argument
1476 	if (cap_write_drain(iommu->cap))  in qi_flush_iotlb()
1479 	if (cap_read_drain(iommu->cap))  in qi_flush_iotlb()
1489 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_iotlb()
1492 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,  in qi_flush_dev_iotlb()  argument
1511 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_dev_iotlb()
1515 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,  in qi_flush_piotlb()  argument
1552 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_piotlb()
1556 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,  in qi_flush_dev_iotlb_pasid()  argument
1596 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_dev_iotlb_pasid()
1599 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did,  in qi_flush_pasid_cache()  argument
1606 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_pasid_cache()
1612 void dmar_disable_qi(struct intel_iommu *iommu)  in dmar_disable_qi()  argument
1618 	if (!ecap_qis(iommu->ecap))  in dmar_disable_qi()
1621 	raw_spin_lock_irqsave(&iommu->register_lock, flags);  in dmar_disable_qi()
1623 	sts =  readl(iommu->reg + DMAR_GSTS_REG);  in dmar_disable_qi()
1630 	while ((readl(iommu->reg + DMAR_IQT_REG) !=  in dmar_disable_qi()
1631 		readl(iommu->reg + DMAR_IQH_REG)) &&  in dmar_disable_qi()
1635 	iommu->gcmd &= ~DMA_GCMD_QIE;  in dmar_disable_qi()
1636 	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);  in dmar_disable_qi()
1638 	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,  in dmar_disable_qi()
1641 	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);  in dmar_disable_qi()
1647 static void __dmar_enable_qi(struct intel_iommu *iommu)  in __dmar_enable_qi()  argument
1651 	struct q_inval *qi = iommu->qi;  in __dmar_enable_qi()
1661 	if (ecap_smts(iommu->ecap))  in __dmar_enable_qi()
1664 	raw_spin_lock_irqsave(&iommu->register_lock, flags);  in __dmar_enable_qi()
1667 	writel(0, iommu->reg + DMAR_IQT_REG);  in __dmar_enable_qi()
1669 	dmar_writeq(iommu->reg + DMAR_IQA_REG, val);  in __dmar_enable_qi()
1671 	iommu->gcmd |= DMA_GCMD_QIE;  in __dmar_enable_qi()
1672 	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);  in __dmar_enable_qi()
1675 	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);  in __dmar_enable_qi()
1677 	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);  in __dmar_enable_qi()
1685 int dmar_enable_qi(struct intel_iommu *iommu)  in dmar_enable_qi()  argument
1690 	if (!ecap_qis(iommu->ecap))  in dmar_enable_qi()
1696 	if (iommu->qi)  in dmar_enable_qi()
1699 	iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);  in dmar_enable_qi()
1700 	if (!iommu->qi)  in dmar_enable_qi()
1703 	qi = iommu->qi;  in dmar_enable_qi()
1709 	desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,  in dmar_enable_qi()
1710 				     !!ecap_smts(iommu->ecap));  in dmar_enable_qi()
1713 		iommu->qi = NULL;  in dmar_enable_qi()
1723 		iommu->qi = NULL;  in dmar_enable_qi()
1729 	__dmar_enable_qi(iommu);  in dmar_enable_qi()
1734 /* iommu interrupt handling. Most stuff are MSI-like. */
1849 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)  in dmar_msi_reg()  argument
1851 	if (iommu->irq == irq)  in dmar_msi_reg()
1853 	else if (iommu->pr_irq == irq)  in dmar_msi_reg()
1861 	struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);  in dmar_msi_unmask()  local
1862 	int reg = dmar_msi_reg(iommu, data->irq);  in dmar_msi_unmask()
1866 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_unmask()
1867 	writel(0, iommu->reg + reg);  in dmar_msi_unmask()
1869 	readl(iommu->reg + reg);  in dmar_msi_unmask()
1870 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_unmask()
1875 	struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);  in dmar_msi_mask()  local
1876 	int reg = dmar_msi_reg(iommu, data->irq);  in dmar_msi_mask()
1880 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_mask()
1881 	writel(DMA_FECTL_IM, iommu->reg + reg);  in dmar_msi_mask()
1883 	readl(iommu->reg + reg);  in dmar_msi_mask()
1884 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_mask()
1889 	struct intel_iommu *iommu = irq_get_handler_data(irq);  in dmar_msi_write()  local
1890 	int reg = dmar_msi_reg(iommu, irq);  in dmar_msi_write()
1893 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_write()
1894 	writel(msg->data, iommu->reg + reg + 4);  in dmar_msi_write()
1895 	writel(msg->address_lo, iommu->reg + reg + 8);  in dmar_msi_write()
1896 	writel(msg->address_hi, iommu->reg + reg + 12);  in dmar_msi_write()
1897 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_write()
1902 	struct intel_iommu *iommu = irq_get_handler_data(irq);  in dmar_msi_read()  local
1903 	int reg = dmar_msi_reg(iommu, irq);  in dmar_msi_read()
1906 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_read()
1907 	msg->data = readl(iommu->reg + reg + 4);  in dmar_msi_read()
1908 	msg->address_lo = readl(iommu->reg + reg + 8);  in dmar_msi_read()
1909 	msg->address_hi = readl(iommu->reg + reg + 12);  in dmar_msi_read()
1910 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_read()
1913 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,  in dmar_fault_do_one()  argument
1944 	dmar_fault_dump_ptes(iommu, source_id, addr, pasid);  in dmar_fault_do_one()
1952 	struct intel_iommu *iommu = dev_id;  in dmar_fault()  local
1960 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_fault()
1961 	fault_status = readl(iommu->reg + DMAR_FSTS_REG);  in dmar_fault()
1970 	reg = cap_fault_reg_offset(iommu->cap);  in dmar_fault()
1983 		data = readl(iommu->reg + reg +  in dmar_fault()
1993 			data = readl(iommu->reg + reg +  in dmar_fault()
1998 			guest_addr = dmar_readq(iommu->reg + reg +  in dmar_fault()
2004 		writel(DMA_FRCD_F, iommu->reg + reg +  in dmar_fault()
2007 		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_fault()
2011 			dmar_fault_do_one(iommu, type, fault_reason,  in dmar_fault()
2016 		if (fault_index >= cap_num_fault_regs(iommu->cap))  in dmar_fault()
2018 		raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_fault()
2022 	       iommu->reg + DMAR_FSTS_REG);  in dmar_fault()
2025 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_fault()
2029 int dmar_set_interrupt(struct intel_iommu *iommu)  in dmar_set_interrupt()  argument
2036 	if (iommu->irq)  in dmar_set_interrupt()
2039 	irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);  in dmar_set_interrupt()
2041 		iommu->irq = irq;  in dmar_set_interrupt()
2047 	ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);  in dmar_set_interrupt()
2056 	struct intel_iommu *iommu;  in enable_drhd_fault_handling()  local
2061 	for_each_iommu(iommu, drhd) {  in enable_drhd_fault_handling()
2063 		int ret = dmar_set_interrupt(iommu);  in enable_drhd_fault_handling()
2074 		dmar_fault(iommu->irq, iommu);  in enable_drhd_fault_handling()
2075 		fault_status = readl(iommu->reg + DMAR_FSTS_REG);  in enable_drhd_fault_handling()
2076 		writel(fault_status, iommu->reg + DMAR_FSTS_REG);  in enable_drhd_fault_handling()
2085 int dmar_reenable_qi(struct intel_iommu *iommu)  in dmar_reenable_qi()  argument
2087 	if (!ecap_qis(iommu->ecap))  in dmar_reenable_qi()
2090 	if (!iommu->qi)  in dmar_reenable_qi()
2096 	dmar_disable_qi(iommu);  in dmar_reenable_qi()
2102 	__dmar_enable_qi(iommu);  in dmar_reenable_qi()