Lines Matching +full:32 +full:- +full:63
1 /* SPDX-License-Identifier: GPL-2.0-only */
88 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
169 #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
170 #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
173 #define Q_ENT(q, p) ((q)->base + \
174 Q_IDX(&((q)->llq), p) * \
175 (q)->ent_dwords)
185 #define Q_MAX_SZ_SHIFT (PAGE_SHIFT + MAX_ORDER - 1)
214 #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
244 #define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32)
285 #define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32)
293 #define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48)
306 #define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT)
326 #define CMDQ_PREFETCH_0_SID GENMASK_ULL(63, 32)
328 #define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12)
331 #define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32)
338 #define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32)
339 #define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48)
343 #define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12)
347 #define CMDQ_ATC_0_SID GENMASK_ULL(63, 32)
350 #define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12)
353 #define CMDQ_PRI_0_SID GENMASK_ULL(63, 32)
361 #define CMDQ_RESUME_0_SID GENMASK_ULL(63, 32)
370 #define CMDQ_SYNC_0_MSIDATA GENMASK_ULL(63, 32)
376 #define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT)
387 #define EVTQ_0_SID GENMASK_ULL(63, 32)
396 #define EVTQ_2_ADDR GENMASK_ULL(63, 0)
402 #define PRIQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT)
405 #define PRIQ_0_SSID GENMASK_ULL(51, 32)
411 #define PRIQ_0_SSID_V (1UL << 63)
414 #define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12)
416 /* High-level queue structures */
434 /* Command-specific fields */
564 /* High-level stream table and context descriptor structures */
780 return -ENODEV; in arm_smmu_master_enable_sva()
785 return -ENODEV; in arm_smmu_master_disable_sva()
796 return ERR_PTR(-ENODEV); in arm_smmu_sva_bind()