Lines Matching refs:reg_width
474 int reg_width; member
488 .reg_width = 8,
496 .reg_width = 8,
504 .reg_width = 1,
512 .reg_width = 1,
519 .reg_width = 1,
526 .reg_width = 1,
533 .reg_width = 3,
542 .reg_width = 1,
549 .reg_width = 4,
557 .reg_width = 4,
565 .reg_width = 2,
573 .reg_width = 2,
581 .reg_width = 5,
589 .reg_width = 5,
597 .reg_width = 10,
605 .reg_width = 2,
613 .reg_width = 1,
620 .reg_width = 1,
627 .reg_width = 1,
634 .reg_width = 1,
641 .reg_width = 1,
648 .reg_width = 2,
656 .reg_width = 8,
665 .reg_width = 5,
674 .reg_width = 3,
683 .reg_width = 5,
691 .reg_width = 4,
699 .reg_width = 5,
707 .reg_width = 5,
715 .reg_width = 10,
724 .reg_width = 4,
733 .reg_width = 4,
742 .reg_width = 8,
752 .reg_width = 8,
761 .reg_width = 8,
769 .reg_width = 4,
777 .reg_width = 4,
785 .reg_width = 4,
793 .reg_width = 4,
801 .reg_width = 4,
809 .reg_width = 4,
817 .reg_width = 8,
826 .reg_width = 1,
834 .reg_width = 3,
843 .reg_width = 1,
851 .reg_width = 3,
859 .reg_width = 8,
867 .reg_width = 8,
876 .reg_width = 8,
886 .reg_width = 5,
896 .reg_width = 8,
906 .reg_width = 8,
915 .reg_width = 1,
922 .reg_width = 16,
931 .reg_width = 16,
939 .reg_width = 16,
947 .reg_width = 16,
956 .reg_width = 16,
964 .reg_width = 16,
973 .reg_width = 16,
981 .reg_width = 16,
1625 int reg_width = iqs7222_props[i].reg_width; in iqs7222_parse_props() local
1646 if (reg_width == 1) { in iqs7222_parse_props()
1656 if (reg_width == 1) { in iqs7222_parse_props()
1673 val_max = GENMASK(reg_width - 1, 0) * val_pitch; in iqs7222_parse_props()
1681 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1, in iqs7222_parse_props()