24 #define IQS7222_PROD_NUM			0x00
29 #define IQS7222_SYS_STATUS			0x10
32 #define IQS7222_SYS_STATUS_ATI_ACTIVE		BIT(0)
39 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK	GENMASK(2, 0)
42 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK	GENMASK(7, 0)
44 #define IQS7222_GPIO_SETUP_0_GPIO_EN		BIT(0)
46 #define IQS7222_SYS_SETUP			0xD0
53 #define IQS7222_SYS_SETUP_ACK_RESET		BIT(0)
58 #define IQS7222_EVENT_MASK_PROX			BIT(0)
60 #define IQS7222_COMMS_HOLD			BIT(0)
61 #define IQS7222_COMMS_ERROR			0xEEEE
81 #define IQS7222_REG_OFFSET			0x100
154 		.mask = BIT(0),
155 		.val = BIT(0),
156 		.enable = BIT(0),
225 				.base = 0x8000,
230 				.base = 0x8700,
235 				.base = 0x9000,
240 				.base = 0xA000,
245 				.base = 0xAC00,
250 				.base = 0xB000,
255 				.base = 0xC000,
279 				.base = 0x8000,
284 				.base = 0x8A00,
289 				.base = 0x9000,
294 				.base = 0xB000,
299 				.base = 0xC400,
321 				.base = 0x8000,
326 				.base = 0x8A00,
331 				.base = 0x9000,
336 				.base = 0xB000,
341 				.base = 0xC400,
368 				.base = 0x8000,
373 				.base = 0x8500,
378 				.base = 0x9000,
383 				.base = 0xA000,
388 				.base = 0xAA00,
393 				.base = 0xB000,
398 				.base = 0xC000,
425 				.base = 0x8000,
430 				.base = 0x8500,
435 				.base = 0x9000,
440 				.base = 0xA000,
445 				.base = 0xAA00,
450 				.base = 0xB000,
455 				.base = 0xC000,
486 		.reg_offset = 0,
494 		.reg_offset = 0,
495 		.reg_shift = 0,
532 		.reg_shift = 0,
556 		.reg_shift = 0,
563 		.reg_offset = 0,
571 		.reg_offset = 0,
588 		.reg_shift = 0,
596 		.reg_shift = 0,
603 		.reg_offset = 0,
611 		.reg_offset = 0,
618 		.reg_offset = 0,
625 		.reg_offset = 0,
632 		.reg_offset = 0,
639 		.reg_offset = 0,
646 		.reg_offset = 0,
647 		.reg_shift = 0,
673 		.reg_shift = 0,
698 		.reg_shift = 0,
714 		.reg_shift = 0,
722 		.reg_offset = 0,
731 		.reg_offset = 0,
740 		.reg_offset = 0,
741 		.reg_shift = 0,
751 		.reg_shift = 0,
767 		.reg_offset = 0,
775 		.reg_offset = 0,
783 		.reg_offset = 0,
791 		.reg_offset = 0,
792 		.reg_shift = 0,
808 		.reg_shift = 0,
815 		.reg_offset = 0,
824 		.reg_offset = 0,
832 		.reg_offset = 0,
841 		.reg_offset = 0,
849 		.reg_offset = 0,
866 		.reg_shift = 0,
905 		.reg_shift = 0,
913 		.reg_offset = 0,
921 		.reg_shift = 0,
930 		.reg_shift = 0,
938 		.reg_shift = 0,
946 		.reg_shift = 0,
955 		.reg_shift = 0,
963 		.reg_shift = 0,
972 		.reg_shift = 0,
980 		.reg_shift = 0,
1049 		if (ret < 0)  in iqs7222_irq_poll()
1051 		else if (ret > 0)  in iqs7222_irq_poll()
1052 			return 0;  in iqs7222_irq_poll()
1053 	} while (ktime_compare(ktime_get(), irq_timeout) < 0);  in iqs7222_irq_poll()
1064 		return 0;  in iqs7222_hard_reset()
1069 	gpiod_set_value_cansleep(iqs7222->reset_gpio, 0);  in iqs7222_hard_reset()
1080 	u8 msg_buf[] = { 0xFF, };  in iqs7222_force_comms()
1086 	 * ever all write data is ignored, and all read data returns 0xEE.  in iqs7222_force_comms()
1097 	if (ret < 0)  in iqs7222_force_comms()
1099 	else if (ret > 0)  in iqs7222_force_comms()
1100 		return 0;  in iqs7222_force_comms()
1104 		if (ret >= 0)  in iqs7222_force_comms()
1127 			.flags = 0,  in iqs7222_read_burst()
1149 	for (i = 0; i < IQS7222_NUM_RETRIES; i++) {  in iqs7222_read_burst()
1151 		if (ret < 0)  in iqs7222_read_burst()
1156 			if (ret >= 0)  in iqs7222_read_burst()
1168 		ret = 0;  in iqs7222_read_burst()
1178 	if (ret < 0)  in iqs7222_read_burst()
1180 			"Failed to read from address 0x%04X: %d\n", reg, ret);  in iqs7222_read_burst()
1196 	return 0;  in iqs7222_read_word()
1229 	for (i = 0; i < IQS7222_NUM_RETRIES; i++) {  in iqs7222_write_burst()
1231 		if (ret < 0)  in iqs7222_write_burst()
1236 			if (ret >= 0)  in iqs7222_write_burst()
1243 		ret = 0;  in iqs7222_write_burst()
1251 	if (ret < 0)  in iqs7222_write_burst()
1253 			"Failed to write to address 0x%04X: %d\n", reg, ret);  in iqs7222_write_burst()
1269 	u16 sys_status = 0;  in iqs7222_ati_trigger()
1286 	for (i = 0; i < IQS7222_NUM_RETRIES; i++) {  in iqs7222_ati_trigger()
1311 				return 0;  in iqs7222_ati_trigger()
1330 		} while (ktime_compare(ktime_get(), ati_timeout) < 0);  in iqs7222_ati_trigger()
1333 			"ATI attempt %d of %d failed with status 0x%02X, %s\n",  in iqs7222_ati_trigger()
1362 					   iqs7222->sys_setup[0] |  in iqs7222_dev_init()
1371 		iqs7222->filt_setup[1] &= GENMASK(7, 0);  in iqs7222_dev_init()
1372 		iqs7222->filt_setup[1] |= (filt_setup & ~GENMASK(7, 0));  in iqs7222_dev_init()
1396 	for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {  in iqs7222_dev_init()
1406 		val = iqs7222_setup(iqs7222, i, 0);  in iqs7222_dev_init()
1414 		for (j = 0; j < num_row; j++) {  in iqs7222_dev_init()
1419 				for (k = 0; k < num_col; k++)  in iqs7222_dev_init()
1424 				for (k = 0; k < num_col; k++)  in iqs7222_dev_init()
1464 		return 0;  in iqs7222_dev_init()
1481 	for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) {  in iqs7222_dev_info()
1482 		if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num)  in iqs7222_dev_info()
1494 		return 0;  in iqs7222_dev_info()
1502 			le16_to_cpu(dev_id[0]));  in iqs7222_dev_info()
1518 		return 0;  in iqs7222_gpio_select()
1521 		return 0;  in iqs7222_gpio_select()
1528 	} else if (count < 0) {  in iqs7222_gpio_select()
1543 	for (i = 0; i < count; i++) {  in iqs7222_gpio_select()
1561 		gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN;  in iqs7222_gpio_select()
1566 	return 0;  in iqs7222_gpio_select()
1602 			return 0;  in iqs7222_parse_props()
1621 	for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) {  in iqs7222_parse_props()
1673 			val_max = GENMASK(reg_width - 1, 0) * val_pitch;  in iqs7222_parse_props()
1686 	return 0;  in iqs7222_parse_props()
1709 		return 0;  in iqs7222_parse_cycle()
1717 		return 0;  in iqs7222_parse_cycle()
1720 	if (count < 0) {  in iqs7222_parse_cycle()
1740 	for (i = 0; i < count; i++) {  in iqs7222_parse_cycle()
1750 	return 0;  in iqs7222_parse_cycle()
1772 		return 0;  in iqs7222_parse_chan()
1778 	chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN;  in iqs7222_parse_chan()
1810 		chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW;  in iqs7222_parse_chan()
1829 		ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;  in iqs7222_parse_chan()
1848 		if (count < 0) {  in iqs7222_parse_chan()
1870 		chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4);  in iqs7222_parse_chan()
1872 		for (i = 0; i < count; i++) {  in iqs7222_parse_chan()
1873 			int min_crx = chan_index < ext_chan / 2 ? 0 : 4;  in iqs7222_parse_chan()
1882 			chan_setup[0] |= BIT(pins[i] + 4 - min_crx);  in iqs7222_parse_chan()
1886 	for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) {  in iqs7222_parse_chan()
1903 					    dev_desc->touch_link - (i ? 0 : 2));  in iqs7222_parse_chan()
2008 		return 0;  in iqs7222_parse_sldr()
2016 	if (count < 0) {  in iqs7222_parse_sldr()
2040 	reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1;  in iqs7222_parse_sldr()
2042 	sldr_setup[0] |= count;  in iqs7222_parse_sldr()
2043 	sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0);  in iqs7222_parse_sldr()
2045 	for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {  in iqs7222_parse_sldr()
2046 		sldr_setup[5 + reg_offset + i] = 0;  in iqs7222_parse_sldr()
2111 		input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0);  in iqs7222_parse_sldr()
2116 		sldr_setup[0] &= ~dev_desc->wheel_enable;  in iqs7222_parse_sldr()
2118 			sldr_setup[0] |= dev_desc->wheel_enable;  in iqs7222_parse_sldr()
2127 		for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++)  in iqs7222_parse_sldr()
2130 	for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) {  in iqs7222_parse_sldr()
2178 		 * coordinate field reports 0xFFFF and solely relies on touch  in iqs7222_parse_sldr()
2213 	for (i = 0; i < reg_grps[IQS7222_REG_GRP_CYCLE].num_row; i++) {  in iqs7222_parse_all()
2219 	error = iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_GLBL,  in iqs7222_parse_all()
2224 	for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) {  in iqs7222_parse_all()
2229 		gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN;  in iqs7222_parse_all()
2230 		gpio_setup[1] = 0;  in iqs7222_parse_all()
2231 		gpio_setup[2] = 0;  in iqs7222_parse_all()
2246 		for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++)  in iqs7222_parse_all()
2247 			gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]);  in iqs7222_parse_all()
2249 		gpio_setup[0] |= BIT(iqs7222_gpio_links[i]);  in iqs7222_parse_all()
2252 	for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {  in iqs7222_parse_all()
2255 		chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK;  in iqs7222_parse_all()
2256 		chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN;  in iqs7222_parse_all()
2258 		chan_setup[5] = 0;  in iqs7222_parse_all()
2261 	for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {  in iqs7222_parse_all()
2267 	error = iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_FILT,  in iqs7222_parse_all()
2272 	for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {  in iqs7222_parse_all()
2275 		sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK;  in iqs7222_parse_all()
2282 	return iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_SYS,  in iqs7222_parse_all()
2300 	if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) {  in iqs7222_report()
2305 	if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) {  in iqs7222_report()
2310 	if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE)  in iqs7222_report()
2311 		return 0;  in iqs7222_report()
2313 	for (i = 0; i < num_chan; i++) {  in iqs7222_report()
2316 		if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN))  in iqs7222_report()
2319 		for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) {  in iqs7222_report()
2340 	for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {  in iqs7222_report()
2345 		if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK))  in iqs7222_report()
2352 		input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0],  in iqs7222_report()
2382 					 iqs7222->sl_code[i][j], 0);  in iqs7222_report()
2387 	return 0;  in iqs7222_report()
2470 	if (irq < 0)  in iqs7222_probe()