Lines Matching +full:0 +full:- +full:32
1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
17 #define IRDMA_IRD_HW_SIZE_4 0
24 IRDMA_ANY_PROTOCOL = 0,
29 #define IRDMA_QP_STATE_INVALID 0
54 #define RDMA_OPCODE_M 0x0f
57 #define CQE_MAJOR_DRV 0x8000
68 #define IRDMA_AE_SOURCE_RSVD 0x0
69 #define IRDMA_AE_SOURCE_RQ 0x1
70 #define IRDMA_AE_SOURCE_RQ_0011 0x3
72 #define IRDMA_AE_SOURCE_CQ 0x2
73 #define IRDMA_AE_SOURCE_CQ_0110 0x6
74 #define IRDMA_AE_SOURCE_CQ_1010 0xa
75 #define IRDMA_AE_SOURCE_CQ_1110 0xe
77 #define IRDMA_AE_SOURCE_SQ 0x5
78 #define IRDMA_AE_SOURCE_SQ_0111 0x7
80 #define IRDMA_AE_SOURCE_IN_RR_WR 0x9
81 #define IRDMA_AE_SOURCE_IN_RR_WR_1011 0xb
82 #define IRDMA_AE_SOURCE_OUT_RR 0xd
83 #define IRDMA_AE_SOURCE_OUT_RR_1111 0xf
85 #define IRDMA_TCP_STATE_NON_EXISTENT 0
122 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
124 #define IRDMAQP_TERM_SEND_TERM_AND_FIN 0
136 #define IRDMA_CQE_QTYPE_RQ 0
140 #define IRDMA_QP_WQE_MIN_SIZE 32
151 #define IRDMAQP_OP_RDMA_WRITE 0x00
152 #define IRDMAQP_OP_RDMA_READ 0x01
153 #define IRDMAQP_OP_RDMA_SEND 0x03
154 #define IRDMAQP_OP_RDMA_SEND_INV 0x04
155 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT 0x05
156 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV 0x06
157 #define IRDMAQP_OP_BIND_MW 0x08
158 #define IRDMAQP_OP_FAST_REGISTER 0x09
159 #define IRDMAQP_OP_LOCAL_INVALIDATE 0x0a
160 #define IRDMAQP_OP_RDMA_READ_LOC_INV 0x0b
161 #define IRDMAQP_OP_NOP 0x0c
162 #define IRDMAQP_OP_RDMA_WRITE_SOL 0x0d
163 #define IRDMAQP_OP_GEN_RTS_AE 0x30
197 IRDMA_OP_AH_DESTROY = 32,
222 #define IRDMA_CQP_OP_CREATE_QP 0
223 #define IRDMA_CQP_OP_MODIFY_QP 0x1
224 #define IRDMA_CQP_OP_DESTROY_QP 0x02
225 #define IRDMA_CQP_OP_CREATE_CQ 0x03
226 #define IRDMA_CQP_OP_MODIFY_CQ 0x04
227 #define IRDMA_CQP_OP_DESTROY_CQ 0x05
228 #define IRDMA_CQP_OP_ALLOC_STAG 0x09
229 #define IRDMA_CQP_OP_REG_MR 0x0a
230 #define IRDMA_CQP_OP_QUERY_STAG 0x0b
231 #define IRDMA_CQP_OP_REG_SMR 0x0c
232 #define IRDMA_CQP_OP_DEALLOC_STAG 0x0d
233 #define IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE 0x0e
234 #define IRDMA_CQP_OP_MANAGE_ARP 0x0f
235 #define IRDMA_CQP_OP_MANAGE_VF_PBLE_BP 0x10
236 #define IRDMA_CQP_OP_MANAGE_PUSH_PAGES 0x11
237 #define IRDMA_CQP_OP_QUERY_RDMA_FEATURES 0x12
238 #define IRDMA_CQP_OP_UPLOAD_CONTEXT 0x13
239 #define IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY 0x14
240 #define IRDMA_CQP_OP_UPLOAD_CONTEXT 0x13
241 #define IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE 0x15
242 #define IRDMA_CQP_OP_CREATE_CEQ 0x16
243 #define IRDMA_CQP_OP_DESTROY_CEQ 0x18
244 #define IRDMA_CQP_OP_CREATE_AEQ 0x19
245 #define IRDMA_CQP_OP_DESTROY_AEQ 0x1b
246 #define IRDMA_CQP_OP_CREATE_ADDR_HANDLE 0x1c
247 #define IRDMA_CQP_OP_MODIFY_ADDR_HANDLE 0x1d
248 #define IRDMA_CQP_OP_DESTROY_ADDR_HANDLE 0x1e
249 #define IRDMA_CQP_OP_UPDATE_PE_SDS 0x1f
250 #define IRDMA_CQP_OP_QUERY_FPM_VAL 0x20
251 #define IRDMA_CQP_OP_COMMIT_FPM_VAL 0x21
252 #define IRDMA_CQP_OP_FLUSH_WQES 0x22
254 #define IRDMA_CQP_OP_GEN_AE 0x22
255 #define IRDMA_CQP_OP_MANAGE_APBVT 0x23
256 #define IRDMA_CQP_OP_NOP 0x24
257 #define IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25
258 #define IRDMA_CQP_OP_CREATE_MCAST_GRP 0x26
259 #define IRDMA_CQP_OP_MODIFY_MCAST_GRP 0x27
260 #define IRDMA_CQP_OP_DESTROY_MCAST_GRP 0x28
261 #define IRDMA_CQP_OP_SUSPEND_QP 0x29
262 #define IRDMA_CQP_OP_RESUME_QP 0x2a
263 #define IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED 0x2b
264 #define IRDMA_CQP_OP_WORK_SCHED_NODE 0x2c
265 #define IRDMA_CQP_OP_MANAGE_STATS 0x2d
266 #define IRDMA_CQP_OP_GATHER_STATS 0x2e
267 #define IRDMA_CQP_OP_UP_MAP 0x2f
270 #define IRDMA_AE_AMP_UNALLOCATED_STAG 0x0102
271 #define IRDMA_AE_AMP_INVALID_STAG 0x0103
272 #define IRDMA_AE_AMP_BAD_QP 0x0104
273 #define IRDMA_AE_AMP_BAD_PD 0x0105
274 #define IRDMA_AE_AMP_BAD_STAG_KEY 0x0106
275 #define IRDMA_AE_AMP_BAD_STAG_INDEX 0x0107
276 #define IRDMA_AE_AMP_BOUNDS_VIOLATION 0x0108
277 #define IRDMA_AE_AMP_RIGHTS_VIOLATION 0x0109
278 #define IRDMA_AE_AMP_TO_WRAP 0x010a
279 #define IRDMA_AE_AMP_FASTREG_VALID_STAG 0x010c
280 #define IRDMA_AE_AMP_FASTREG_MW_STAG 0x010d
281 #define IRDMA_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e
282 #define IRDMA_AE_AMP_FASTREG_INVALID_LENGTH 0x0110
283 #define IRDMA_AE_AMP_INVALIDATE_SHARED 0x0111
284 #define IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112
285 #define IRDMA_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113
286 #define IRDMA_AE_AMP_MWBIND_VALID_STAG 0x0114
287 #define IRDMA_AE_AMP_MWBIND_OF_MR_STAG 0x0115
288 #define IRDMA_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116
289 #define IRDMA_AE_AMP_MWBIND_TO_MW_STAG 0x0117
290 #define IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118
291 #define IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119
292 #define IRDMA_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a
293 #define IRDMA_AE_AMP_MWBIND_BIND_DISABLED 0x011b
294 #define IRDMA_AE_PRIV_OPERATION_DENIED 0x011c
295 #define IRDMA_AE_AMP_INVALIDATE_TYPE1_MW 0x011d
296 #define IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW 0x011e
297 #define IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG 0x011f
298 #define IRDMA_AE_AMP_MWBIND_WRONG_TYPE 0x0120
299 #define IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH 0x0121
300 #define IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132
301 #define IRDMA_AE_UDA_XMIT_BAD_PD 0x0133
302 #define IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134
303 #define IRDMA_AE_UDA_L4LEN_INVALID 0x0135
304 #define IRDMA_AE_BAD_CLOSE 0x0201
305 #define IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202
306 #define IRDMA_AE_CQ_OPERATION_ERROR 0x0203
307 #define IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205
308 #define IRDMA_AE_STAG_ZERO_INVALID 0x0206
309 #define IRDMA_AE_IB_RREQ_AND_Q1_FULL 0x0207
310 #define IRDMA_AE_IB_INVALID_REQUEST 0x0208
311 #define IRDMA_AE_WQE_UNEXPECTED_OPCODE 0x020a
312 #define IRDMA_AE_WQE_INVALID_PARAMETER 0x020b
313 #define IRDMA_AE_WQE_INVALID_FRAG_DATA 0x020c
314 #define IRDMA_AE_IB_REMOTE_ACCESS_ERROR 0x020d
315 #define IRDMA_AE_IB_REMOTE_OP_ERROR 0x020e
316 #define IRDMA_AE_WQE_LSMM_TOO_LONG 0x0220
317 #define IRDMA_AE_INVALID_REQUEST 0x0223
318 #define IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301
319 #define IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303
320 #define IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304
321 #define IRDMA_AE_DDP_UBE_INVALID_MO 0x0305
322 #define IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306
323 #define IRDMA_AE_DDP_UBE_INVALID_QN 0x0307
324 #define IRDMA_AE_DDP_NO_L_BIT 0x0308
325 #define IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311
326 #define IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312
327 #define IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313
328 #define IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314
329 #define IRDMA_AE_ROCE_RSP_LENGTH_ERROR 0x0316
330 #define IRDMA_AE_ROCE_EMPTY_MCG 0x0380
331 #define IRDMA_AE_ROCE_BAD_MC_IP_ADDR 0x0381
332 #define IRDMA_AE_ROCE_BAD_MC_QPID 0x0382
333 #define IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH 0x0383
334 #define IRDMA_AE_INVALID_ARP_ENTRY 0x0401
335 #define IRDMA_AE_INVALID_TCP_OPTION_RCVD 0x0402
336 #define IRDMA_AE_STALE_ARP_ENTRY 0x0403
337 #define IRDMA_AE_INVALID_AH_ENTRY 0x0406
338 #define IRDMA_AE_LLP_CLOSE_COMPLETE 0x0501
339 #define IRDMA_AE_LLP_CONNECTION_RESET 0x0502
340 #define IRDMA_AE_LLP_FIN_RECEIVED 0x0503
341 #define IRDMA_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504
342 #define IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505
343 #define IRDMA_AE_LLP_SEGMENT_TOO_SMALL 0x0507
344 #define IRDMA_AE_LLP_SYN_RECEIVED 0x0508
345 #define IRDMA_AE_LLP_TERMINATE_RECEIVED 0x0509
346 #define IRDMA_AE_LLP_TOO_MANY_RETRIES 0x050a
347 #define IRDMA_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b
348 #define IRDMA_AE_LLP_DOUBT_REACHABILITY 0x050c
349 #define IRDMA_AE_LLP_CONNECTION_ESTABLISHED 0x050e
350 #define IRDMA_AE_RESOURCE_EXHAUSTION 0x0520
351 #define IRDMA_AE_RESET_SENT 0x0601
352 #define IRDMA_AE_TERMINATE_SENT 0x0602
353 #define IRDMA_AE_RESET_NOT_SENT 0x0603
354 #define IRDMA_AE_LCE_QP_CATASTROPHIC 0x0700
355 #define IRDMA_AE_LCE_FUNCTION_CATASTROPHIC 0x0701
356 #define IRDMA_AE_LCE_CQ_CATASTROPHIC 0x0702
357 #define IRDMA_AE_QP_SUSPEND_COMPLETE 0x0900
360 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
362 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
364 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
366 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
368 #define IRDMA_STATS_DELTA(a, b, c) ((a) >= (b) ? (a) - (b) : (a) + (c) - (b))
369 #define IRDMA_MAX_STATS_32 0xFFFFFFFFULL
370 #define IRDMA_MAX_STATS_48 0xFFFFFFFFFFFFULL
372 #define IRDMA_MAX_CQ_READ_THRESH 0x3FFFF
373 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
374 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
375 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
377 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
378 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
379 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
380 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
381 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
383 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
392 #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
393 #define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)
394 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(5, 0)
404 #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
406 #define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(9, 0)
408 #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
413 #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
414 #define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(5, 0)
415 #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
417 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)
418 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
419 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
421 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)
428 #define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)
429 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
431 #define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)
434 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
435 #define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)
437 #define IRDMA_CQPHC_HW_MAJVER_GEN_1 0
441 #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
443 #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
445 #define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)
449 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
450 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
451 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
452 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
460 #define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)
462 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
464 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
474 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
477 #define IRDMA_CQ_IMMDATA_S 0
478 #define IRDMA_CQ_IMMDATA_M (0xffffffffffffffffULL << IRDMA_CQ_IMMVALID_S)
479 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
480 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
481 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
482 #define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32)
483 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
484 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
486 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
493 #define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)
498 #define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)
500 #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
510 #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
513 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
520 #define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)
523 #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
526 #define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)
527 #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
529 #define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)
538 #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
543 #define IRDMA_CQPSQ_QP_QPID_S 0
544 #define IRDMA_CQPSQ_QP_QPID_M (0xFFFFFFUL)
546 #define IRDMA_CQPSQ_QP_OP_S 32
567 #define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)
568 #define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)
569 #define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0)
571 #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
579 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
583 #define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)
584 #define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)
587 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
601 #define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(5, 0)
603 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
605 #define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)
608 #define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)
612 #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
614 #define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)
615 #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
616 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)
620 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)
622 #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
626 /* Manage Push Page - MPP */
627 #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff
628 #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff
630 #define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(9, 0)
631 #define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(9, 0)
636 /* Upload Context - UCTX */
638 #define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)
644 #define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)
647 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)
648 #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
649 #define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)
650 #define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)
655 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
656 #define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)
659 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
661 #define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0)
663 #define IRDMA_COMMIT_FPM_BASE_S 32
664 #define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(5, 0)
665 #define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)
667 #define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)
669 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
671 #define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)
676 #define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)
678 #define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)
679 #define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)
680 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
681 #define IRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)
684 #define IRDMA_CQPSQ_UPESD_BM_PF 0
688 #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
689 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)
691 #define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)
692 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)
693 #define IRDMA_CQPSQ_RESUMEQP_QPID GENMASK(23, 0)
695 #define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001
696 #define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005
698 #define IRDMA_CQPSQ_MAJ_NO_ERROR 0x0000
699 #define IRDMA_CQPSQ_MAJ_OBJCACHE_ERROR 0xF000
700 #define IRDMA_CQPSQ_MAJ_CNTXTCACHE_ERROR 0xF001
701 #define IRDMA_CQPSQ_MAJ_ERROR 0xFFFF
702 #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
723 #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
730 #define IRDMAQPC_TTL GENMASK_ULL(7, 0)
736 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
738 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
739 #define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)
740 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
741 #define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)
744 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
746 #define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)
752 #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
756 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
758 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
759 #define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)
762 #define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)
763 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
764 #define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)
765 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
766 #define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)
767 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
768 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
769 #define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)
770 #define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
771 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
772 #define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)
773 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
774 #define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)
775 #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
776 #define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
777 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
778 #define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)
779 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
780 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
781 #define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)
782 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
783 #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(45, 32)
785 #define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)
788 #define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0)
789 #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)
790 #define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)
792 #define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)
794 #define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)
810 #define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
811 #define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)
817 #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
821 #define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)
824 #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
825 #define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)
826 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
827 #define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)
828 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
829 #define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)
831 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
832 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
835 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
850 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
851 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
852 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
853 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
854 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
855 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
856 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
857 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)
865 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
866 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
875 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
876 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
880 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
882 #define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)
887 #define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)
889 #define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)
904 #define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(18, 0)
905 #define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(19, 0)
906 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)
907 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)
908 #define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)
909 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
910 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
912 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
913 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
914 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
915 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
916 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(5, 0)
920 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
925 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
930 (_ceq)->ceqe_base[_pos].buf \
938 #define IRDMA_CQP_INIT_WQE(wqe) memset(wqe, 0, 64)
942 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
947 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
952 (_ring).head = 0; \
953 (_ring).tail = 0; \
966 (_retcode) = 0; \
968 (_retcode) = -ENOMEM; \
977 (_retcode) = 0; \
979 (_retcode) = -ENOMEM; \
988 (_retcode) = 0; \
990 (_retcode) = -ENOMEM; \
997 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
999 (_retcode) = 0; \
1001 (_retcode) = -ENOMEM; \
1021 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \
1026 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \
1031 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \
1036 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \
1041 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \
1045 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \
1049 (IRDMA_RING_USED_QUANTA(_ring) != 0) \
1054 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1059 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1064 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1074 IRDMA_WQE_SIZE_32 = 32,
1082 IRDMA_ADD_NODE = 0,
1087 enum { IRDMA_Q_ALIGNMENT_M = (128 - 1),
1088 IRDMA_AEQ_ALIGNMENT_M = (256 - 1),
1089 IRDMA_Q2_ALIGNMENT_M = (256 - 1),
1090 IRDMA_CEQ_ALIGNMENT_M = (256 - 1),
1091 IRDMA_CQ0_ALIGNMENT_M = (256 - 1),
1092 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1),
1093 IRDMA_SHADOWAREA_M = (128 - 1),
1094 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1),
1095 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1099 IRDMA_CQP_ALIGNMENT = 0x200,
1100 IRDMA_AEQ_ALIGNMENT = 0x100,
1101 IRDMA_CEQ_ALIGNMENT = 0x100,
1102 IRDMA_CQ0_ALIGNMENT = 0x100,
1103 IRDMA_SD_BUF_ALIGNMENT = 0x80,
1104 IRDMA_FEATURE_BUF_ALIGNMENT = 0x8,
1108 ICRDMA_ANY_PROTOCOL = 0,
1114 * set_64bit_val - set 64 bit value to hw wqe
1125 * set_32bit_val - set 32 bit value to hw wqe
1136 * get_64bit_val - read 64 bit value from wqe
1147 * get_32bit_val - read 32 bit value from wqe
1150 * @val: return 32 bit value