6302 	struct hns_roce_eq_context *eqc;  in config_eqc()  local
6306 	eqc = mb_buf;  in config_eqc()
6307 	memset(eqc, 0, sizeof(struct hns_roce_eq_context));  in config_eqc()
6319 	hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);  in config_eqc()
6320 	hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);  in config_eqc()
6321 	hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);  in config_eqc()
6322 	hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);  in config_eqc()
6323 	hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);  in config_eqc()
6324 	hr_reg_write(eqc, EQC_EQN, eq->eqn);  in config_eqc()
6325 	hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);  in config_eqc()
6326 	hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,  in config_eqc()
6328 	hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,  in config_eqc()
6330 	hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);  in config_eqc()
6331 	hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);  in config_eqc()
6342 	hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);  in config_eqc()
6343 	hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);  in config_eqc()
6344 	hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);  in config_eqc()
6345 	hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);  in config_eqc()
6346 	hr_reg_write(eqc, EQC_SHIFT, eq->shift);  in config_eqc()
6347 	hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);  in config_eqc()
6348 	hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);  in config_eqc()
6349 	hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);  in config_eqc()
6350 	hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);  in config_eqc()
6351 	hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);  in config_eqc()
6352 	hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);  in config_eqc()
6353 	hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);  in config_eqc()
6354 	hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);  in config_eqc()