1377 		if (vl == CNTR_INVALID_VL)  in dev_access_u32_csr()
1381 		if (vl != CNTR_INVALID_VL)  in dev_access_u32_csr()
1437 		if (vl == CNTR_INVALID_VL)  in dev_access_u64_csr()
1441 		if (vl != CNTR_INVALID_VL)  in dev_access_u64_csr()
1456 	if (vl != CNTR_INVALID_VL)  in dc_access_lcb_cntr()
1478 	if (vl != CNTR_INVALID_VL)  in port_access_u32_csr()
1491 		if (vl == CNTR_INVALID_VL)  in port_access_u64_csr()
1495 		if (vl != CNTR_INVALID_VL)  in port_access_u64_csr()
1528 	if (vl != CNTR_INVALID_VL)  in access_sw_link_dn_cnt()
1538 	if (vl != CNTR_INVALID_VL)  in access_sw_link_up_cnt()
1549 	if (vl != CNTR_INVALID_VL)  in access_sw_unknown_frame_cnt()
1561 	if (vl == CNTR_INVALID_VL)  in access_sw_xmit_discards()
1577 	if (vl != CNTR_INVALID_VL)  in access_xmit_constraint_errs()
1589 	if (vl != CNTR_INVALID_VL)  in access_rcv_constraint_errs()
1612 	if (vl != CNTR_INVALID_VL)  in read_write_cpu()
4070 	if (vl != CNTR_INVALID_VL)					      \
5552 	u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);  in update_rcverr_timer()
12240 							CNTR_INVALID_VL,  in hfi1_read_cntrs()
12292 						       CNTR_INVALID_VL,  in hfi1_read_portcntrs()
12430 	if (vl != CNTR_INVALID_VL)  in read_dev_cntr()
12444 	if (vl != CNTR_INVALID_VL)  in write_dev_cntr()
12458 	if (vl != CNTR_INVALID_VL)  in read_port_cntr()
12478 	if (vl != CNTR_INVALID_VL)  in write_port_cntr()
12509 	cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);  in do_update_synth_timer()
12512 	cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);  in do_update_synth_timer()
12547 				read_dev_cntr(dd, i, CNTR_INVALID_VL);  in do_update_synth_timer()
12558 					read_port_cntr(ppd, j, CNTR_INVALID_VL);  in do_update_synth_timer()
12570 		dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,  in do_update_synth_timer()
12574 		dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,  in do_update_synth_timer()