1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/iio/timer/stm32-timer-trigger.h>
13 #include <linux/mfd/stm32-timers.h>
126 	div = (unsigned long long)clk_get_rate(priv->clk);  in stm32_timer_start()
136 	while (div > priv->max_arr) {  in stm32_timer_start()
144 		dev_err(priv->dev, "prescaler exceeds the maximum value\n");  in stm32_timer_start()
145 		return -EINVAL;  in stm32_timer_start()
149 	regmap_read(priv->regmap, TIM_CCER, &ccer);  in stm32_timer_start()
151 		return -EBUSY;  in stm32_timer_start()
153 	mutex_lock(&priv->lock);  in stm32_timer_start()
154 	if (!priv->enabled) {  in stm32_timer_start()
155 		priv->enabled = true;  in stm32_timer_start()
156 		clk_enable(priv->clk);  in stm32_timer_start()
159 	regmap_write(priv->regmap, TIM_PSC, prescaler);  in stm32_timer_start()
160 	regmap_write(priv->regmap, TIM_ARR, prd - 1);  in stm32_timer_start()
161 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);  in stm32_timer_start()
164 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_timer_start()
165 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,  in stm32_timer_start()
168 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,  in stm32_timer_start()
172 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);  in stm32_timer_start()
175 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);  in stm32_timer_start()
176 	mutex_unlock(&priv->lock);  in stm32_timer_start()
186 	regmap_read(priv->regmap, TIM_CCER, &ccer);  in stm32_timer_stop()
190 	mutex_lock(&priv->lock);  in stm32_timer_stop()
192 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);  in stm32_timer_stop()
193 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_timer_stop()
194 	regmap_write(priv->regmap, TIM_PSC, 0);  in stm32_timer_stop()
195 	regmap_write(priv->regmap, TIM_ARR, 0);  in stm32_timer_stop()
198 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_timer_stop()
199 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);  in stm32_timer_stop()
201 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);  in stm32_timer_stop()
204 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);  in stm32_timer_stop()
206 	if (priv->enabled) {  in stm32_timer_stop()
207 		priv->enabled = false;  in stm32_timer_stop()
208 		clk_disable(priv->clk);  in stm32_timer_stop()
210 	mutex_unlock(&priv->lock);  in stm32_timer_stop()
245 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_tt_read_frequency()
246 	regmap_read(priv->regmap, TIM_PSC, &psc);  in stm32_tt_read_frequency()
247 	regmap_read(priv->regmap, TIM_ARR, &arr);  in stm32_tt_read_frequency()
250 		freq = (unsigned long long)clk_get_rate(priv->clk);  in stm32_tt_read_frequency()
293 	regmap_read(priv->regmap, TIM_CR2, &cr2);  in stm32_tt_show_master_mode()
295 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_tt_show_master_mode()
312 	if (stm32_timer_is_trgo2_name(trig->name)) {  in stm32_tt_store_master_mode()
325 			mutex_lock(&priv->lock);  in stm32_tt_store_master_mode()
326 			if (!priv->enabled) {  in stm32_tt_store_master_mode()
328 				priv->enabled = true;  in stm32_tt_store_master_mode()
329 				clk_enable(priv->clk);  in stm32_tt_store_master_mode()
331 			regmap_update_bits(priv->regmap, TIM_CR2, mask,  in stm32_tt_store_master_mode()
333 			mutex_unlock(&priv->lock);  in stm32_tt_store_master_mode()
338 	return -EINVAL;  in stm32_tt_store_master_mode()
349 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_tt_show_master_mode_avail()
355 		len += scnprintf(buf + len, PAGE_SIZE - len,  in stm32_tt_show_master_mode_avail()
359 	buf[len - 1] = '\n';  in stm32_tt_show_master_mode_avail()
395 	list_for_each_entry(tr, &priv->tr_list, alloc_list)  in stm32_unregister_iio_triggers()
402 	const char * const *cur = priv->triggers;  in stm32_register_iio_triggers()
404 	INIT_LIST_HEAD(&priv->tr_list);  in stm32_register_iio_triggers()
411 		if (cur_is_trgo2 && !priv->has_trgo2) {  in stm32_register_iio_triggers()
416 		trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);  in stm32_register_iio_triggers()
418 			return -ENOMEM;  in stm32_register_iio_triggers()
420 		trig->dev.parent = priv->dev->parent;  in stm32_register_iio_triggers()
421 		trig->ops = &timer_trigger_ops;  in stm32_register_iio_triggers()
428 			trig->dev.groups = stm32_trigger_attr_groups;  in stm32_register_iio_triggers()
438 		list_add_tail(&trig->alloc_list, &priv->tr_list);  in stm32_register_iio_triggers()
454 		regmap_read(priv->regmap, TIM_CNT, &dat);  in stm32_counter_read_raw()
459 		regmap_read(priv->regmap, TIM_CR1, &dat);  in stm32_counter_read_raw()
464 		regmap_read(priv->regmap, TIM_SMCR, &dat);  in stm32_counter_read_raw()
477 	return -EINVAL;  in stm32_counter_read_raw()
488 		return regmap_write(priv->regmap, TIM_CNT, val);  in stm32_counter_write_raw()
492 		return -EINVAL;  in stm32_counter_write_raw()
495 		mutex_lock(&priv->lock);  in stm32_counter_write_raw()
497 			if (!priv->enabled) {  in stm32_counter_write_raw()
498 				priv->enabled = true;  in stm32_counter_write_raw()
499 				clk_enable(priv->clk);  in stm32_counter_write_raw()
501 			regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,  in stm32_counter_write_raw()
504 			regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,  in stm32_counter_write_raw()
506 			if (priv->enabled) {  in stm32_counter_write_raw()
507 				priv->enabled = false;  in stm32_counter_write_raw()
508 				clk_disable(priv->clk);  in stm32_counter_write_raw()
511 		mutex_unlock(&priv->lock);  in stm32_counter_write_raw()
515 	return -EINVAL;  in stm32_counter_write_raw()
522 	const char * const *cur = priv->valids;  in stm32_counter_validate_trigger()
526 		return -EINVAL;  in stm32_counter_validate_trigger()
529 		if (!strncmp(trig->name, *cur, strlen(trig->name))) {  in stm32_counter_validate_trigger()
530 			regmap_update_bits(priv->regmap,  in stm32_counter_validate_trigger()
539 	return -EINVAL;  in stm32_counter_validate_trigger()
558 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);  in stm32_set_trigger_mode()
569 	regmap_read(priv->regmap, TIM_SMCR, &smcr);  in stm32_get_trigger_mode()
571 	return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;  in stm32_get_trigger_mode()
598 	return -EINVAL;  in stm32_enable_mode2sms()
614 	mutex_lock(&priv->lock);  in stm32_set_enable_mode()
615 	if (sms == 6 && !priv->enabled) {  in stm32_set_enable_mode()
616 		clk_enable(priv->clk);  in stm32_set_enable_mode()
617 		priv->enabled = true;  in stm32_set_enable_mode()
619 	mutex_unlock(&priv->lock);  in stm32_set_enable_mode()
621 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);  in stm32_set_enable_mode()
637 	return -EINVAL;  in stm32_sms2enable_mode()
646 	regmap_read(priv->regmap, TIM_SMCR, &smcr);  in stm32_get_enable_mode()
667 	regmap_read(priv->regmap, TIM_ARR, &arr);  in stm32_count_get_preset()
686 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);  in stm32_count_set_preset()
687 	regmap_write(priv->regmap, TIM_ARR, preset);  in stm32_count_set_preset()
726 	indio_dev->name = dev_name(dev);  in stm32_setup_counter_device()
727 	indio_dev->info = &stm32_trigger_info;  in stm32_setup_counter_device()
728 	indio_dev->modes = INDIO_HARDWARE_TRIGGERED;  in stm32_setup_counter_device()
729 	indio_dev->num_channels = 1;  in stm32_setup_counter_device()
730 	indio_dev->channels = &stm32_trigger_channel;  in stm32_setup_counter_device()
743  * return true if the trigger is a valid stm32 iio timer trigger
748 	return (trig->ops == &timer_trigger_ops);  in is_stm32_timer_trigger()
760 	regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);  in stm32_timer_detect_trgo2()
761 	regmap_read(priv->regmap, TIM_CR2, &val);  in stm32_timer_detect_trgo2()
762 	regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);  in stm32_timer_detect_trgo2()
763 	priv->has_trgo2 = !!val;  in stm32_timer_detect_trgo2()
768 	struct device *dev = &pdev->dev;  in stm32_timer_trigger_probe()
770 	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);  in stm32_timer_trigger_probe()
782 	    index >= cfg->num_valids_table)  in stm32_timer_trigger_probe()
783 		return -EINVAL;  in stm32_timer_trigger_probe()
786 	if (*cfg->valids_table[index])  in stm32_timer_trigger_probe()
792 		return -ENOMEM;  in stm32_timer_trigger_probe()
794 	priv->dev = dev;  in stm32_timer_trigger_probe()
795 	priv->regmap = ddata->regmap;  in stm32_timer_trigger_probe()
796 	priv->clk = ddata->clk;  in stm32_timer_trigger_probe()
797 	priv->max_arr = ddata->max_arr;  in stm32_timer_trigger_probe()
798 	priv->triggers = triggers_table[index];  in stm32_timer_trigger_probe()
799 	priv->valids = cfg->valids_table[index];  in stm32_timer_trigger_probe()
801 	mutex_init(&priv->lock);  in stm32_timer_trigger_probe()
821 	regmap_read(priv->regmap, TIM_CCER, &val);  in stm32_timer_trigger_remove()
823 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_timer_trigger_remove()
825 	if (priv->enabled)  in stm32_timer_trigger_remove()
826 		clk_disable(priv->clk);  in stm32_timer_trigger_remove()
836 	if (priv->enabled) {  in stm32_timer_trigger_suspend()
838 		regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);  in stm32_timer_trigger_suspend()
839 		regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2);  in stm32_timer_trigger_suspend()
840 		regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc);  in stm32_timer_trigger_suspend()
841 		regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);  in stm32_timer_trigger_suspend()
842 		regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);  in stm32_timer_trigger_suspend()
843 		regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);  in stm32_timer_trigger_suspend()
846 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_timer_trigger_suspend()
847 		clk_disable(priv->clk);  in stm32_timer_trigger_suspend()
858 	if (priv->enabled) {  in stm32_timer_trigger_resume()
859 		ret = clk_enable(priv->clk);  in stm32_timer_trigger_resume()
864 		regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);  in stm32_timer_trigger_resume()
865 		regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2);  in stm32_timer_trigger_resume()
868 		regmap_write(priv->regmap, TIM_PSC, priv->bak.psc);  in stm32_timer_trigger_resume()
869 		regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);  in stm32_timer_trigger_resume()
870 		regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);  in stm32_timer_trigger_resume()
872 		/* Also re-enables the timer */  in stm32_timer_trigger_resume()
873 		regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);  in stm32_timer_trigger_resume()
895 		.compatible = "st,stm32-timer-trigger",
898 		.compatible = "st,stm32h7-timer-trigger",
909 		.name = "stm32-timer-trigger",
916 MODULE_ALIAS("platform:stm32-timer-trigger");
917 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");