123 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,  in xadc_write_reg()  argument
126 	writel(val, xadc->base + reg);  in xadc_write_reg()
129 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,  in xadc_read_reg()  argument
132 	*val = readl(xadc->base + reg);  in xadc_read_reg()
145 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,  in xadc_zynq_write_fifo()  argument
151 		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);  in xadc_zynq_write_fifo()
154 static void xadc_zynq_drain_fifo(struct xadc *xadc)  in xadc_zynq_drain_fifo()  argument
158 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);  in xadc_zynq_drain_fifo()
161 		xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);  in xadc_zynq_drain_fifo()
162 		xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);  in xadc_zynq_drain_fifo()
166 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,  in xadc_zynq_update_intmsk()  argument
169 	xadc->zynq_intmask &= ~mask;  in xadc_zynq_update_intmsk()
170 	xadc->zynq_intmask |= val;  in xadc_zynq_update_intmsk()
172 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,  in xadc_zynq_update_intmsk()
173 		xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_update_intmsk()
176 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_zynq_write_adc_reg()  argument
183 	spin_lock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
184 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_write_adc_reg()
187 	reinit_completion(&xadc->completion);  in xadc_zynq_write_adc_reg()
190 	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));  in xadc_zynq_write_adc_reg()
191 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);  in xadc_zynq_write_adc_reg()
194 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);  in xadc_zynq_write_adc_reg()
196 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);  in xadc_zynq_write_adc_reg()
197 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
199 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_write_adc_reg()
205 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);  in xadc_zynq_write_adc_reg()
210 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_zynq_read_adc_reg()  argument
220 	spin_lock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
221 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_read_adc_reg()
223 	xadc_zynq_drain_fifo(xadc);  in xadc_zynq_read_adc_reg()
224 	reinit_completion(&xadc->completion);  in xadc_zynq_read_adc_reg()
226 	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));  in xadc_zynq_read_adc_reg()
227 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);  in xadc_zynq_read_adc_reg()
230 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);  in xadc_zynq_read_adc_reg()
232 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);  in xadc_zynq_read_adc_reg()
233 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
234 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_read_adc_reg()
240 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);  in xadc_zynq_read_adc_reg()
241 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);  in xadc_zynq_read_adc_reg()
265 	struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);  in xadc_zynq_unmask_worker()  local
268 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);  in xadc_zynq_unmask_worker()
272 	spin_lock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
275 	unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;  in xadc_zynq_unmask_worker()
276 	xadc->zynq_masked_alarm &= misc_sts;  in xadc_zynq_unmask_worker()
279 	xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;  in xadc_zynq_unmask_worker()
282 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);  in xadc_zynq_unmask_worker()
284 	xadc_zynq_update_intmsk(xadc, 0, 0);  in xadc_zynq_unmask_worker()
286 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
289 	if (xadc->zynq_masked_alarm) {  in xadc_zynq_unmask_worker()
290 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_unmask_worker()
299 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_zynq_interrupt_handler()  local
302 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);  in xadc_zynq_interrupt_handler()
304 	status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_interrupt_handler()
309 	spin_lock(&xadc->lock);  in xadc_zynq_interrupt_handler()
311 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);  in xadc_zynq_interrupt_handler()
314 		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_interrupt_handler()
316 		complete(&xadc->completion);  in xadc_zynq_interrupt_handler()
321 		xadc->zynq_masked_alarm |= status;  in xadc_zynq_interrupt_handler()
326 		xadc_zynq_update_intmsk(xadc, 0, 0);  in xadc_zynq_interrupt_handler()
332 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_interrupt_handler()
335 	spin_unlock(&xadc->lock);  in xadc_zynq_interrupt_handler()
347 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_zynq_setup()  local
359 	xadc->zynq_intmask = ~0;  in xadc_zynq_setup()
361 	pcap_rate = clk_get_rate(xadc->clk);  in xadc_zynq_setup()
366 		ret = clk_set_rate(xadc->clk,  in xadc_zynq_setup()
389 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);  in xadc_zynq_setup()
390 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);  in xadc_zynq_setup()
391 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);  in xadc_zynq_setup()
392 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);  in xadc_zynq_setup()
393 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |  in xadc_zynq_setup()
398 		ret = clk_set_rate(xadc->clk, pcap_rate);  in xadc_zynq_setup()
406 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)  in xadc_zynq_get_dclk_rate()  argument
411 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);  in xadc_zynq_get_dclk_rate()
428 	return clk_get_rate(xadc->clk) / div;  in xadc_zynq_get_dclk_rate()
431 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)  in xadc_zynq_update_alarm()  argument
439 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_zynq_update_alarm()
442 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);  in xadc_zynq_update_alarm()
443 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);  in xadc_zynq_update_alarm()
445 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,  in xadc_zynq_update_alarm()
448 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_zynq_update_alarm()
466 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_axi_read_adc_reg()  argument
471 	xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,  in xadc_axi_read_adc_reg()
478 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_axi_write_adc_reg()  argument
481 	xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,  in xadc_axi_write_adc_reg()
490 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_axi_setup()  local
492 	xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);  in xadc_axi_setup()
493 	xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);  in xadc_axi_setup()
501 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_axi_interrupt_handler()  local
505 	xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);  in xadc_axi_interrupt_handler()
506 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);  in xadc_axi_interrupt_handler()
512 	if ((status & XADC_AXI_INT_EOS) && xadc->trigger)  in xadc_axi_interrupt_handler()
513 		iio_trigger_poll(xadc->trigger);  in xadc_axi_interrupt_handler()
528 	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);  in xadc_axi_interrupt_handler()
533 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)  in xadc_axi_update_alarm()  argument
547 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_axi_update_alarm()
548 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);  in xadc_axi_update_alarm()
551 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);  in xadc_axi_update_alarm()
552 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_axi_update_alarm()
555 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)  in xadc_axi_get_dclk()  argument
557 	return clk_get_rate(xadc->clk);  in xadc_axi_get_dclk()
582 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,  in _xadc_update_adc_reg()  argument
588 	ret = _xadc_read_adc_reg(xadc, reg, &tmp);  in _xadc_update_adc_reg()
592 	return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);  in _xadc_update_adc_reg()
595 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_update_adc_reg()  argument
600 	mutex_lock(&xadc->mutex);  in xadc_update_adc_reg()
601 	ret = _xadc_update_adc_reg(xadc, reg, mask, val);  in xadc_update_adc_reg()
602 	mutex_unlock(&xadc->mutex);  in xadc_update_adc_reg()
607 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)  in xadc_get_dclk_rate()  argument
609 	return xadc->ops->get_dclk_rate(xadc);  in xadc_get_dclk_rate()
615 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_update_scan_mode()  local
621 	if (check_mul_overflow(n, sizeof(*xadc->data), &new_size))  in xadc_update_scan_mode()
624 	data = devm_krealloc(indio_dev->dev.parent, xadc->data,  in xadc_update_scan_mode()
630 	xadc->data = data;  in xadc_update_scan_mode()
667 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_trigger_handler()  local
671 	if (!xadc->data)  in xadc_trigger_handler()
678 		xadc_read_adc_reg(xadc, chan, &xadc->data[j]);  in xadc_trigger_handler()
682 	iio_push_to_buffers(indio_dev, xadc->data);  in xadc_trigger_handler()
692 	struct xadc *xadc = iio_trigger_get_drvdata(trigger);  in xadc_trigger_set_state()  local
698 	mutex_lock(&xadc->mutex);  in xadc_trigger_set_state()
702 		if (xadc->trigger != NULL) {  in xadc_trigger_set_state()
706 			xadc->trigger = trigger;  in xadc_trigger_set_state()
707 			if (trigger == xadc->convst_trigger)  in xadc_trigger_set_state()
712 		ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,  in xadc_trigger_set_state()
717 		xadc->trigger = NULL;  in xadc_trigger_set_state()
720 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_trigger_set_state()
721 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);  in xadc_trigger_set_state()
722 	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);  in xadc_trigger_set_state()
727 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);  in xadc_trigger_set_state()
728 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_trigger_set_state()
731 	mutex_unlock(&xadc->mutex);  in xadc_trigger_set_state()
762 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)  in xadc_power_adc_b()  argument
772 	if (xadc->ops->type == XADC_TYPE_US)  in xadc_power_adc_b()
786 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,  in xadc_power_adc_b()
790 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)  in xadc_get_seq_mode()  argument
795 	if (xadc->ops->type == XADC_TYPE_US)  in xadc_get_seq_mode()
798 	if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)  in xadc_get_seq_mode()
810 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_postdisable()  local
820 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);  in xadc_postdisable()
824 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);  in xadc_postdisable()
828 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_postdisable()
833 	return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);  in xadc_postdisable()
838 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_preenable()  local
843 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_preenable()
849 	seq_mode = xadc_get_seq_mode(xadc, scan_mask);  in xadc_preenable()
851 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);  in xadc_preenable()
865 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);  in xadc_preenable()
869 	ret = xadc_power_adc_b(xadc, seq_mode);  in xadc_preenable()
873 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_preenable()
889 static int xadc_read_samplerate(struct xadc *xadc)  in xadc_read_samplerate()  argument
895 	ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);  in xadc_read_samplerate()
903 	return xadc_get_dclk_rate(xadc) / div / 26;  in xadc_read_samplerate()
909 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_read_raw()  local
918 		ret = xadc_read_adc_reg(xadc, chan->address, &val16);  in xadc_read_raw()
963 		ret = xadc_read_samplerate(xadc);  in xadc_read_raw()
974 static int xadc_write_samplerate(struct xadc *xadc, int val)  in xadc_write_samplerate()  argument
976 	unsigned long clk_rate = xadc_get_dclk_rate(xadc);  in xadc_write_samplerate()
1007 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,  in xadc_write_samplerate()
1014 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_write_raw()  local
1019 	return xadc_write_samplerate(xadc, val);  in xadc_write_raw()
1189 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_parse_dt()  local
1205 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;  in xadc_parse_dt()
1207 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;  in xadc_parse_dt()
1209 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;  in xadc_parse_dt()
1213 	if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {  in xadc_parse_dt()
1218 		if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {  in xadc_parse_dt()
1234 	if (xadc->ops->type == XADC_TYPE_S7) {  in xadc_parse_dt()
1313 	struct xadc *xadc;  in xadc_probe()  local
1327 	indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));  in xadc_probe()
1331 	xadc = iio_priv(indio_dev);  in xadc_probe()
1332 	xadc->ops = ops;  in xadc_probe()
1333 	init_completion(&xadc->completion);  in xadc_probe()
1334 	mutex_init(&xadc->mutex);  in xadc_probe()
1335 	spin_lock_init(&xadc->lock);  in xadc_probe()
1336 	INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);  in xadc_probe()
1338 	xadc->base = devm_platform_ioremap_resource(pdev, 0);  in xadc_probe()
1339 	if (IS_ERR(xadc->base))  in xadc_probe()
1340 		return PTR_ERR(xadc->base);  in xadc_probe()
1342 	indio_dev->name = xadc_type_names[xadc->ops->type];  in xadc_probe()
1350 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_probe()
1359 			xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");  in xadc_probe()
1360 			if (IS_ERR(xadc->convst_trigger))  in xadc_probe()
1361 				return PTR_ERR(xadc->convst_trigger);  in xadc_probe()
1363 			xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,  in xadc_probe()
1365 			if (IS_ERR(xadc->samplerate_trigger))  in xadc_probe()
1366 				return PTR_ERR(xadc->samplerate_trigger);  in xadc_probe()
1370 	xadc->clk = devm_clk_get_enabled(dev, NULL);  in xadc_probe()
1371 	if (IS_ERR(xadc->clk))  in xadc_probe()
1372 		return PTR_ERR(xadc->clk);  in xadc_probe()
1378 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_probe()
1379 		ret = xadc_read_samplerate(xadc);  in xadc_probe()
1384 			ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);  in xadc_probe()
1391 		ret = devm_request_irq(dev, irq, xadc->ops->interrupt_handler,  in xadc_probe()
1397 					       &xadc->zynq_unmask_work);  in xadc_probe()
1402 	ret = xadc->ops->setup(pdev, indio_dev, irq);  in xadc_probe()
1407 		xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),  in xadc_probe()
1408 			&xadc->threshold[i]);  in xadc_probe()
1410 	ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);  in xadc_probe()
1420 	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);  in xadc_probe()
1424 	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),  in xadc_probe()
1430 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,  in xadc_probe()
1442 			xadc->threshold[i] = 0xffff;  in xadc_probe()
1444 			xadc->threshold[i] = 0;  in xadc_probe()
1445 		ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),  in xadc_probe()
1446 			xadc->threshold[i]);  in xadc_probe()