1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
11 #include <linux/dma-mapping.h>
15 #include <linux/iio/timer/stm32-lptim-trigger.h>
16 #include <linux/iio/timer/stm32-timer-trigger.h>
25 #include <linux/nvmem-consumer.h>
30 #include "stm32-adc-core.h"
32 /* Number of linear calibration shadow registers / LINCALRDYW control bits */
57 /* extsel - trigger mux selection value */
83 	STM32_ADC_INT_CH_NONE = -1,
91  * struct stm32_adc_ic - ADC internal channels
107  * struct stm32_adc_trig_info - ADC trigger info
117  * struct stm32_adc_calib - optional adc calibration data
118  * @calfact_s: Calibration offset for single ended channels
119  * @calfact_d: Calibration offset in differential
120  * @lincalfact: Linearity calibration factor
121  * @calibrated: Indicates calibration status
131  * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
143  * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data
144  * @vrefint_cal:	vrefint calibration value from nvmem
153  * struct stm32_adc_regspec - stm32 registers definition
154  * @dr:			data register offset
189  * struct stm32_adc_cfg - stm32 compatible configuration data
195  * @prepare:		optional prepare routine (power-up, enable)
198  * @unprepare:		optional unprepare routine (disable, power-down)
219  * struct stm32_adc - private data of each ADC IIO instance
220  * @common:		reference to ADC block common data
222  * @cfg:		compatible configuration data
224  * @buffer:		data buffer + 8 bytes for timestamp if enabled
228  * @bufi:		data buffer index
230  * @res:		data resolution (e.g. RES bitfield value)
236  * @difsel:		bitmask to set single-ended/differential channel
239  * @cal:		optional calibration data on some devices
240  * @vrefint:		internal reference voltage data
280  * struct stm32_adc_info - stm32 ADC, per instance config data
316  * stm32f4_sq - describe regular sequence registers
317  * - L: sequence len (register & bit field)
318  * - SQ1..SQ16: sequence entries (register & bit field)
363  * stm32f4_smp_bits[] - describe sampling time register index & bit fields
456  * stm32h7_smp_bits - describe sampling time register index & bit fields
532 	return readl_relaxed(adc->common->base + adc->offset + reg);  in stm32_adc_readl()
543 	return readw_relaxed(adc->common->base + adc->offset + reg);  in stm32_adc_readw()
548 	writel_relaxed(val, adc->common->base + adc->offset + reg);  in stm32_adc_writel()
555 	spin_lock_irqsave(&adc->lock, flags);  in stm32_adc_set_bits()
557 	spin_unlock_irqrestore(&adc->lock, flags);  in stm32_adc_set_bits()
562 	spin_lock(&adc->common->lock);  in stm32_adc_set_bits_common()
563 	writel_relaxed(readl_relaxed(adc->common->base + reg) | bits,  in stm32_adc_set_bits_common()
564 		       adc->common->base + reg);  in stm32_adc_set_bits_common()
565 	spin_unlock(&adc->common->lock);  in stm32_adc_set_bits_common()
572 	spin_lock_irqsave(&adc->lock, flags);  in stm32_adc_clr_bits()
574 	spin_unlock_irqrestore(&adc->lock, flags);  in stm32_adc_clr_bits()
579 	spin_lock(&adc->common->lock);  in stm32_adc_clr_bits_common()
580 	writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits,  in stm32_adc_clr_bits_common()
581 		       adc->common->base + reg);  in stm32_adc_clr_bits_common()
582 	spin_unlock(&adc->common->lock);  in stm32_adc_clr_bits_common()
586  * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
591 	stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,  in stm32_adc_conv_irq_enable()
592 			   adc->cfg->regs->ier_eoc.mask);  in stm32_adc_conv_irq_enable()
596  * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
601 	stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,  in stm32_adc_conv_irq_disable()
602 			   adc->cfg->regs->ier_eoc.mask);  in stm32_adc_conv_irq_disable()
607 	stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg,  in stm32_adc_ovr_irq_enable()
608 			   adc->cfg->regs->ier_ovr.mask);  in stm32_adc_ovr_irq_enable()
613 	stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg,  in stm32_adc_ovr_irq_disable()
614 			   adc->cfg->regs->ier_ovr.mask);  in stm32_adc_ovr_irq_disable()
619 	const struct stm32_adc_regs *res = &adc->cfg->regs->res;  in stm32_adc_set_res()
622 	val = stm32_adc_readl(adc, res->reg);  in stm32_adc_set_res()
623 	val = (val & ~res->mask) | (adc->res << res->shift);  in stm32_adc_set_res()
624 	stm32_adc_writel(adc, res->reg, val);  in stm32_adc_set_res()
632 	if (adc->cfg->unprepare)  in stm32_adc_hw_stop()
633 		adc->cfg->unprepare(indio_dev);  in stm32_adc_hw_stop()
635 	clk_disable_unprepare(adc->clk);  in stm32_adc_hw_stop()
646 	ret = clk_prepare_enable(adc->clk);  in stm32_adc_hw_start()
652 	if (adc->cfg->prepare) {  in stm32_adc_hw_start()
653 		ret = adc->cfg->prepare(indio_dev);  in stm32_adc_hw_start()
661 	clk_disable_unprepare(adc->clk);  in stm32_adc_hw_start()
672 		if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE)  in stm32_adc_int_ch_enable()
677 			dev_dbg(&indio_dev->dev, "Enable VDDCore\n");  in stm32_adc_int_ch_enable()
678 			stm32_adc_set_bits(adc, adc->cfg->regs->or_vdd.reg,  in stm32_adc_int_ch_enable()
679 					   adc->cfg->regs->or_vdd.mask);  in stm32_adc_int_ch_enable()
682 			dev_dbg(&indio_dev->dev, "Enable VREFInt\n");  in stm32_adc_int_ch_enable()
683 			stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg,  in stm32_adc_int_ch_enable()
684 						  adc->cfg->regs->ccr_vref.mask);  in stm32_adc_int_ch_enable()
687 			dev_dbg(&indio_dev->dev, "Enable VBAT\n");  in stm32_adc_int_ch_enable()
688 			stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg,  in stm32_adc_int_ch_enable()
689 						  adc->cfg->regs->ccr_vbat.mask);  in stm32_adc_int_ch_enable()
700 		if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE)  in stm32_adc_int_ch_disable()
705 			stm32_adc_clr_bits(adc, adc->cfg->regs->or_vdd.reg,  in stm32_adc_int_ch_disable()
706 					   adc->cfg->regs->or_vdd.mask);  in stm32_adc_int_ch_disable()
709 			stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg,  in stm32_adc_int_ch_disable()
710 						  adc->cfg->regs->ccr_vref.mask);  in stm32_adc_int_ch_disable()
713 			stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg,  in stm32_adc_int_ch_disable()
714 						  adc->cfg->regs->ccr_vbat.mask);  in stm32_adc_int_ch_disable()
721  * stm32f4_adc_start_conv() - Start conversions for regular channels.
742 	/* Wait for Power-up time (tSTAB from datasheet) */  in stm32f4_adc_start_conv()
766 	stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);  in stm32f4_adc_irq_clear()
781 	spin_lock_irqsave(&adc->lock, flags);  in stm32h7_adc_start_conv()
785 	spin_unlock_irqrestore(&adc->lock, flags);  in stm32h7_adc_start_conv()
802 		dev_warn(&indio_dev->dev, "stop failed\n");  in stm32h7_adc_stop_conv()
811 	stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);  in stm32h7_adc_irq_clear()
824 	if (adc->common->rate > STM32H7_BOOST_CLKRATE)  in stm32h7_adc_exit_pwr_down()
828 	if (!adc->cfg->has_vregready) {  in stm32h7_adc_exit_pwr_down()
838 		dev_err(&indio_dev->dev, "Failed to exit power down\n");  in stm32h7_adc_exit_pwr_down()
866 		dev_err(&indio_dev->dev, "Failed to enable ADC\n");  in stm32h7_adc_enable()
890 		dev_warn(&indio_dev->dev, "Failed to disable\n");  in stm32h7_adc_disable()
894  * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
904 	/* Read linearity calibration */  in stm32h7_adc_read_selfcalib()
906 	for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {  in stm32h7_adc_read_selfcalib()
910 		/* Poll: wait calib data to be ready in CALFACT2 register */  in stm32h7_adc_read_selfcalib()
915 			dev_err(&indio_dev->dev, "Failed to read calfact\n");  in stm32h7_adc_read_selfcalib()
920 		adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);  in stm32h7_adc_read_selfcalib()
921 		adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;  in stm32h7_adc_read_selfcalib()
926 	/* Read offset calibration */  in stm32h7_adc_read_selfcalib()
928 	adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);  in stm32h7_adc_read_selfcalib()
929 	adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;  in stm32h7_adc_read_selfcalib()
930 	adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);  in stm32h7_adc_read_selfcalib()
931 	adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;  in stm32h7_adc_read_selfcalib()
932 	adc->cal.calibrated = true;  in stm32h7_adc_read_selfcalib()
938  * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
940  * Note: ADC must be enabled, with no on-going conversions.
948 	val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |  in stm32h7_adc_restore_selfcalib()
949 		(adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);  in stm32h7_adc_restore_selfcalib()
953 	for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {  in stm32h7_adc_restore_selfcalib()
955 		 * Write saved calibration data to shadow registers:  in stm32h7_adc_restore_selfcalib()
957 		 * data write. Then poll to wait for complete transfer.  in stm32h7_adc_restore_selfcalib()
959 		val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;  in stm32h7_adc_restore_selfcalib()
966 			dev_err(&indio_dev->dev, "Failed to write calfact\n");  in stm32h7_adc_restore_selfcalib()
971 		 * Read back calibration data, has two effects:  in stm32h7_adc_restore_selfcalib()
972 		 * - It ensures bits LINCALRDYW[6..1] are kept cleared  in stm32h7_adc_restore_selfcalib()
973 		 *   for next time calibration needs to be restored.  in stm32h7_adc_restore_selfcalib()
974 		 * - BTW, bit clear triggers a read, then check data has been  in stm32h7_adc_restore_selfcalib()
982 			dev_err(&indio_dev->dev, "Failed to read calfact\n");  in stm32h7_adc_restore_selfcalib()
986 		if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {  in stm32h7_adc_restore_selfcalib()
987 			dev_err(&indio_dev->dev, "calfact not consistent\n");  in stm32h7_adc_restore_selfcalib()
988 			return -EIO;  in stm32h7_adc_restore_selfcalib()
998  * Fixed timeout value for ADC calibration.
1000  * - low clock frequency
1001  * - maximum prescalers
1002  * Calibration requires:
1003  * - 131,072 ADC clock cycle for the linear calibration
1004  * - 20 ADC clock cycle for the offset calibration
1011  * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
1021 	if (adc->cal.calibrated)  in stm32h7_adc_selfcalib()
1024 	/* ADC must be disabled for calibration */  in stm32h7_adc_selfcalib()
1028 	 * Select calibration mode:  in stm32h7_adc_selfcalib()
1029 	 * - Offset calibration for single ended inputs  in stm32h7_adc_selfcalib()
1030 	 * - No linearity calibration (do it later, before reading it)  in stm32h7_adc_selfcalib()
1035 	/* Start calibration, then wait for completion */  in stm32h7_adc_selfcalib()
1041 		dev_err(&indio_dev->dev, "calibration failed\n");  in stm32h7_adc_selfcalib()
1046 	 * Select calibration mode, then start calibration:  in stm32h7_adc_selfcalib()
1047 	 * - Offset calibration for differential input  in stm32h7_adc_selfcalib()
1048 	 * - Linearity calibration (needs to be done only once for single/diff)  in stm32h7_adc_selfcalib()
1049 	 *   will run simultaneously with offset calibration.  in stm32h7_adc_selfcalib()
1058 		dev_err(&indio_dev->dev, "calibration failed\n");  in stm32h7_adc_selfcalib()
1070  * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
1075  * Restore calibration data.
1076  * Pre-select channels that may be used in PCSEL (required by input MUX / IO):
1077  * - Only one input is selected for single ended (e.g. 'vinp')
1078  * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn')
1096 	stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel);  in stm32h7_adc_prepare()
1102 	/* Either restore or read calibration result for future reference */  in stm32h7_adc_prepare()
1110 	stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);  in stm32h7_adc_prepare()
1135  * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
1149 	const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;  in stm32_adc_conf_scan_seq()
1155 	stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);  in stm32_adc_conf_scan_seq()
1156 	stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);  in stm32_adc_conf_scan_seq()
1158 	for_each_set_bit(bit, scan_mask, indio_dev->masklength) {  in stm32_adc_conf_scan_seq()
1159 		chan = indio_dev->channels + bit;  in stm32_adc_conf_scan_seq()
1166 			return -EINVAL;  in stm32_adc_conf_scan_seq()
1168 		dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",  in stm32_adc_conf_scan_seq()
1169 			__func__, chan->channel, i);  in stm32_adc_conf_scan_seq()
1173 		val |= chan->channel << sqr[i].shift;  in stm32_adc_conf_scan_seq()
1178 		return -EINVAL;  in stm32_adc_conf_scan_seq()
1183 	val |= ((i - 1) << sqr[0].shift);  in stm32_adc_conf_scan_seq()
1190  * stm32_adc_get_trig_extsel() - Get external trigger selection
1194  * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
1203 	for (i = 0; adc->cfg->trigs[i].name; i++) {  in stm32_adc_get_trig_extsel()
1210 		    !strcmp(adc->cfg->trigs[i].name, trig->name)) {  in stm32_adc_get_trig_extsel()
1211 			return adc->cfg->trigs[i].extsel;  in stm32_adc_get_trig_extsel()
1215 	return -EINVAL;  in stm32_adc_get_trig_extsel()
1219  * stm32_adc_set_trig() - Set a regular trigger
1224  * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
1225  * - if HW trigger enabled, set source & polarity
1242 		exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;  in stm32_adc_set_trig()
1245 	spin_lock_irqsave(&adc->lock, flags);  in stm32_adc_set_trig()
1246 	val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);  in stm32_adc_set_trig()
1247 	val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);  in stm32_adc_set_trig()
1248 	val |= exten << adc->cfg->regs->exten.shift;  in stm32_adc_set_trig()
1249 	val |= extsel << adc->cfg->regs->extsel.shift;  in stm32_adc_set_trig()
1250 	stm32_adc_writel(adc,  adc->cfg->regs->exten.reg, val);  in stm32_adc_set_trig()
1251 	spin_unlock_irqrestore(&adc->lock, flags);  in stm32_adc_set_trig()
1262 	adc->trigger_polarity = type;  in stm32_adc_set_trig_pol()
1272 	return adc->trigger_polarity;  in stm32_adc_get_trig_pol()
1276 	"rising-edge", "falling-edge", "both-edges",
1287  * stm32_adc_single_conv() - Performs a single conversion
1293  * - Apply sampling time settings
1294  * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1295  * - Use SW trigger
1296  * - Start conversion, then wait for interrupt completion.
1303 	struct device *dev = indio_dev->dev.parent;  in stm32_adc_single_conv()
1304 	const struct stm32_adc_regspec *regs = adc->cfg->regs;  in stm32_adc_single_conv()
1309 	reinit_completion(&adc->completion);  in stm32_adc_single_conv()
1311 	adc->bufi = 0;  in stm32_adc_single_conv()
1318 	stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);  in stm32_adc_single_conv()
1319 	stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);  in stm32_adc_single_conv()
1322 	val = stm32_adc_readl(adc, regs->sqr[1].reg);  in stm32_adc_single_conv()
1323 	val &= ~regs->sqr[1].mask;  in stm32_adc_single_conv()
1324 	val |= chan->channel << regs->sqr[1].shift;  in stm32_adc_single_conv()
1325 	stm32_adc_writel(adc, regs->sqr[1].reg, val);  in stm32_adc_single_conv()
1328 	stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);  in stm32_adc_single_conv()
1331 	stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);  in stm32_adc_single_conv()
1335 	adc->cfg->start_conv(indio_dev, false);  in stm32_adc_single_conv()
1338 					&adc->completion, STM32_ADC_TIMEOUT);  in stm32_adc_single_conv()
1340 		ret = -ETIMEDOUT;  in stm32_adc_single_conv()
1344 		*res = adc->buffer[0];  in stm32_adc_single_conv()
1348 	adc->cfg->stop_conv(indio_dev);  in stm32_adc_single_conv()
1371 		if (chan->type == IIO_VOLTAGE)  in stm32_adc_read_raw()
1374 			ret = -EINVAL;  in stm32_adc_read_raw()
1377 			*val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val;  in stm32_adc_read_raw()
1383 		if (chan->differential) {  in stm32_adc_read_raw()
1384 			*val = adc->common->vref_mv * 2;  in stm32_adc_read_raw()
1385 			*val2 = chan->scan_type.realbits;  in stm32_adc_read_raw()
1387 			*val = adc->common->vref_mv;  in stm32_adc_read_raw()
1388 			*val2 = chan->scan_type.realbits;  in stm32_adc_read_raw()
1393 		if (chan->differential)  in stm32_adc_read_raw()
1395 			*val = -((1 << chan->scan_type.realbits) / 2);  in stm32_adc_read_raw()
1401 		return -EINVAL;  in stm32_adc_read_raw()
1409 	adc->cfg->irq_clear(indio_dev, msk);  in stm32_adc_irq_clear()
1412 static irqreturn_t stm32_adc_threaded_isr(int irq, void *data)  in stm32_adc_threaded_isr()  argument
1414 	struct iio_dev *indio_dev = data;  in stm32_adc_threaded_isr()
1416 	const struct stm32_adc_regspec *regs = adc->cfg->regs;  in stm32_adc_threaded_isr()
1417 	u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);  in stm32_adc_threaded_isr()
1420 	if (status & regs->isr_ovr.mask) {  in stm32_adc_threaded_isr()
1426 		adc->cfg->stop_conv(indio_dev);  in stm32_adc_threaded_isr()
1427 		stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask);  in stm32_adc_threaded_isr()
1428 		dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n");  in stm32_adc_threaded_isr()
1435 static irqreturn_t stm32_adc_isr(int irq, void *data)  in stm32_adc_isr()  argument
1437 	struct iio_dev *indio_dev = data;  in stm32_adc_isr()
1439 	const struct stm32_adc_regspec *regs = adc->cfg->regs;  in stm32_adc_isr()
1440 	u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);  in stm32_adc_isr()
1442 	if (status & regs->isr_ovr.mask) {  in stm32_adc_isr()
1444 		 * Overrun occurred on regular conversions: data for wrong  in stm32_adc_isr()
1446 		 * to stop processing data and print error message.  in stm32_adc_isr()
1448 		 * re-enabling it (e.g. write 0, then 1 to buffer/enable).  in stm32_adc_isr()
1455 	if (status & regs->isr_eoc.mask) {  in stm32_adc_isr()
1457 		adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);  in stm32_adc_isr()
1459 			adc->bufi++;  in stm32_adc_isr()
1460 			if (adc->bufi >= adc->num_conv) {  in stm32_adc_isr()
1462 				iio_trigger_poll(indio_dev->trig);  in stm32_adc_isr()
1465 			complete(&adc->completion);  in stm32_adc_isr()
1474  * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1479  * driver, -EINVAL otherwise.
1484 	return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0;  in stm32_adc_validate_trigger()
1496 	 * - always one buffer (period) dma is working on  in stm32_adc_set_watermark()
1497 	 * - one buffer (period) driver can push data.  in stm32_adc_set_watermark()
1500 	adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);  in stm32_adc_set_watermark()
1509 	struct device *dev = indio_dev->dev.parent;  in stm32_adc_update_scan_mode()
1516 	adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);  in stm32_adc_update_scan_mode()
1530 	for (i = 0; i < indio_dev->num_channels; i++)  in stm32_adc_fwnode_xlate()
1531 		if (indio_dev->channels[i].channel == iiospec->args[0])  in stm32_adc_fwnode_xlate()
1534 	return -EINVAL;  in stm32_adc_fwnode_xlate()
1538  * stm32_adc_debugfs_reg_access - read or write register value
1556 	struct device *dev = indio_dev->dev.parent;  in stm32_adc_debugfs_reg_access()
1588 	status = dmaengine_tx_status(adc->dma_chan,  in stm32_adc_dma_residue()
1589 				     adc->dma_chan->cookie,  in stm32_adc_dma_residue()
1593 		unsigned int i = adc->rx_buf_sz - state.residue;  in stm32_adc_dma_residue()
1597 		if (i >= adc->bufi)  in stm32_adc_dma_residue()
1598 			size = i - adc->bufi;  in stm32_adc_dma_residue()
1600 			size = adc->rx_buf_sz + i - adc->bufi;  in stm32_adc_dma_residue()
1608 static void stm32_adc_dma_buffer_done(void *data)  in stm32_adc_dma_buffer_done()  argument
1610 	struct iio_dev *indio_dev = data;  in stm32_adc_dma_buffer_done()
1618 	 * relevant as the conversions have already been done. Data  in stm32_adc_dma_buffer_done()
1623 	dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);  in stm32_adc_dma_buffer_done()
1625 	while (residue >= indio_dev->scan_bytes) {  in stm32_adc_dma_buffer_done()
1626 		u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];  in stm32_adc_dma_buffer_done()
1630 		residue -= indio_dev->scan_bytes;  in stm32_adc_dma_buffer_done()
1631 		adc->bufi += indio_dev->scan_bytes;  in stm32_adc_dma_buffer_done()
1632 		if (adc->bufi >= adc->rx_buf_sz)  in stm32_adc_dma_buffer_done()
1633 			adc->bufi = 0;  in stm32_adc_dma_buffer_done()
1644 	if (!adc->dma_chan)  in stm32_adc_dma_start()
1647 	dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,  in stm32_adc_dma_start()
1648 		adc->rx_buf_sz, adc->rx_buf_sz / 2);  in stm32_adc_dma_start()
1651 	desc = dmaengine_prep_dma_cyclic(adc->dma_chan,  in stm32_adc_dma_start()
1652 					 adc->rx_dma_buf,  in stm32_adc_dma_start()
1653 					 adc->rx_buf_sz, adc->rx_buf_sz / 2,  in stm32_adc_dma_start()
1657 		return -EBUSY;  in stm32_adc_dma_start()
1659 	desc->callback = stm32_adc_dma_buffer_done;  in stm32_adc_dma_start()
1660 	desc->callback_param = indio_dev;  in stm32_adc_dma_start()
1665 		dmaengine_terminate_sync(adc->dma_chan);  in stm32_adc_dma_start()
1670 	dma_async_issue_pending(adc->dma_chan);  in stm32_adc_dma_start()
1678 	struct device *dev = indio_dev->dev.parent;  in stm32_adc_buffer_postenable()
1685 	ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);  in stm32_adc_buffer_postenable()
1687 		dev_err(&indio_dev->dev, "Can't set trigger\n");  in stm32_adc_buffer_postenable()
1693 		dev_err(&indio_dev->dev, "Can't start dma\n");  in stm32_adc_buffer_postenable()
1698 	adc->bufi = 0;  in stm32_adc_buffer_postenable()
1702 	if (!adc->dma_chan)  in stm32_adc_buffer_postenable()
1705 	adc->cfg->start_conv(indio_dev, !!adc->dma_chan);  in stm32_adc_buffer_postenable()
1721 	struct device *dev = indio_dev->dev.parent;  in stm32_adc_buffer_predisable()
1723 	adc->cfg->stop_conv(indio_dev);  in stm32_adc_buffer_predisable()
1724 	if (!adc->dma_chan)  in stm32_adc_buffer_predisable()
1729 	if (adc->dma_chan)  in stm32_adc_buffer_predisable()
1730 		dmaengine_terminate_sync(adc->dma_chan);  in stm32_adc_buffer_predisable()
1733 		dev_err(&indio_dev->dev, "Can't clear trigger\n");  in stm32_adc_buffer_predisable()
1749 	struct iio_dev *indio_dev = pf->indio_dev;  in stm32_adc_trigger_handler()
1752 	dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);  in stm32_adc_trigger_handler()
1755 	adc->bufi = 0;  in stm32_adc_trigger_handler()
1756 	iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,  in stm32_adc_trigger_handler()
1757 					   pf->timestamp);  in stm32_adc_trigger_handler()
1758 	iio_trigger_notify_done(indio_dev->trig);  in stm32_adc_trigger_handler()
1760 	/* re-enable eoc irq */  in stm32_adc_trigger_handler()
1779 	struct device *dev = &indio_dev->dev;  in stm32_adc_fw_get_resolution()
1784 	if (device_property_read_u32(dev, "assigned-resolution-bits", &res))  in stm32_adc_fw_get_resolution()
1785 		res = adc->cfg->adc_info->resolutions[0];  in stm32_adc_fw_get_resolution()
1787 	for (i = 0; i < adc->cfg->adc_info->num_res; i++)  in stm32_adc_fw_get_resolution()
1788 		if (res == adc->cfg->adc_info->resolutions[i])  in stm32_adc_fw_get_resolution()
1790 	if (i >= adc->cfg->adc_info->num_res) {  in stm32_adc_fw_get_resolution()
1791 		dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);  in stm32_adc_fw_get_resolution()
1792 		return -EINVAL;  in stm32_adc_fw_get_resolution()
1795 	dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res);  in stm32_adc_fw_get_resolution()
1796 	adc->res = i;  in stm32_adc_fw_get_resolution()
1803 	const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];  in stm32_adc_smpr_init()
1804 	u32 period_ns, shift = smpr->shift, mask = smpr->mask;  in stm32_adc_smpr_init()
1805 	unsigned int smp, r = smpr->reg;  in stm32_adc_smpr_init()
1811 	if (channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT])  in stm32_adc_smpr_init()
1812 		smp_ns = max(smp_ns, adc->cfg->ts_vrefint_ns);  in stm32_adc_smpr_init()
1815 	period_ns = NSEC_PER_SEC / adc->common->rate;  in stm32_adc_smpr_init()
1817 		if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)  in stm32_adc_smpr_init()
1822 	/* pre-build sampling time registers (e.g. smpr1, smpr2) */  in stm32_adc_smpr_init()
1823 	adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);  in stm32_adc_smpr_init()
1831 	char *name = adc->chan_name[vinp];  in stm32_adc_chan_init_one()
1833 	chan->type = IIO_VOLTAGE;  in stm32_adc_chan_init_one()
1834 	chan->channel = vinp;  in stm32_adc_chan_init_one()
1836 		chan->differential = 1;  in stm32_adc_chan_init_one()
1837 		chan->channel2 = vinn;  in stm32_adc_chan_init_one()
1838 		snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn);  in stm32_adc_chan_init_one()
1842 	chan->datasheet_name = name;  in stm32_adc_chan_init_one()
1843 	chan->scan_index = scan_index;  in stm32_adc_chan_init_one()
1844 	chan->indexed = 1;  in stm32_adc_chan_init_one()
1845 	if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT])  in stm32_adc_chan_init_one()
1846 		chan->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED);  in stm32_adc_chan_init_one()
1848 		chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);  in stm32_adc_chan_init_one()
1849 	chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  in stm32_adc_chan_init_one()
1851 	chan->scan_type.sign = 'u';  in stm32_adc_chan_init_one()
1852 	chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];  in stm32_adc_chan_init_one()
1853 	chan->scan_type.storagebits = 16;  in stm32_adc_chan_init_one()
1854 	chan->ext_info = stm32_adc_ext_info;  in stm32_adc_chan_init_one()
1856 	/* pre-build selected channels mask */  in stm32_adc_chan_init_one()
1857 	adc->pcsel |= BIT(chan->channel);  in stm32_adc_chan_init_one()
1859 		/* pre-build diff channels mask */  in stm32_adc_chan_init_one()
1860 		adc->difsel |= BIT(chan->channel);  in stm32_adc_chan_init_one()
1861 		/* Also add negative input to pre-selected channels */  in stm32_adc_chan_init_one()
1862 		adc->pcsel |= BIT(chan->channel2);  in stm32_adc_chan_init_one()
1868 	struct device *dev = &indio_dev->dev;  in stm32_adc_get_legacy_chan_count()
1869 	const struct stm32_adc_info *adc_info = adc->cfg->adc_info;  in stm32_adc_get_legacy_chan_count()
1872 	ret = device_property_count_u32(dev, "st,adc-channels");  in stm32_adc_get_legacy_chan_count()
1873 	if (ret > adc_info->max_channels) {  in stm32_adc_get_legacy_chan_count()
1874 		dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");  in stm32_adc_get_legacy_chan_count()
1875 		return -EINVAL;  in stm32_adc_get_legacy_chan_count()
1881 	 * each st,adc-diff-channels is a group of 2 u32 so we divide @ret  in stm32_adc_get_legacy_chan_count()
1884 	ret = device_property_count_u32(dev, "st,adc-diff-channels");  in stm32_adc_get_legacy_chan_count()
1889 	if (ret > adc_info->max_channels) {  in stm32_adc_get_legacy_chan_count()
1890 		dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n");  in stm32_adc_get_legacy_chan_count()
1891 		return -EINVAL;  in stm32_adc_get_legacy_chan_count()
1893 		adc->num_diff = ret;  in stm32_adc_get_legacy_chan_count()
1898 	adc->nsmps = device_property_count_u32(dev, "st,min-sample-time-nsecs");  in stm32_adc_get_legacy_chan_count()
1899 	if (adc->nsmps > 1 && adc->nsmps != num_channels) {  in stm32_adc_get_legacy_chan_count()
1900 		dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");  in stm32_adc_get_legacy_chan_count()
1901 		return -EINVAL;  in stm32_adc_get_legacy_chan_count()
1912 	const struct stm32_adc_info *adc_info = adc->cfg->adc_info;  in stm32_adc_legacy_chan_init()
1914 	struct device *dev = &indio_dev->dev;  in stm32_adc_legacy_chan_init()
1915 	u32 num_diff = adc->num_diff;  in stm32_adc_legacy_chan_init()
1921 		ret = device_property_read_u32_array(dev, "st,adc-diff-channels",  in stm32_adc_legacy_chan_init()
1924 			dev_err(&indio_dev->dev, "Failed to get diff channels %d\n", ret);  in stm32_adc_legacy_chan_init()
1929 			if (diff[i].vinp >= adc_info->max_channels ||  in stm32_adc_legacy_chan_init()
1930 			    diff[i].vinn >= adc_info->max_channels) {  in stm32_adc_legacy_chan_init()
1931 				dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n",  in stm32_adc_legacy_chan_init()
1933 				return -EINVAL;  in stm32_adc_legacy_chan_init()
1943 	ret = device_property_read_u32_array(dev, "st,adc-channels", chans,  in stm32_adc_legacy_chan_init()
1949 		if (chans[c] >= adc_info->max_channels) {  in stm32_adc_legacy_chan_init()
1950 			dev_err(&indio_dev->dev, "Invalid channel %d\n",  in stm32_adc_legacy_chan_init()
1952 			return -EINVAL;  in stm32_adc_legacy_chan_init()
1955 		/* Channel can't be configured both as single-ended & diff */  in stm32_adc_legacy_chan_init()
1958 				dev_err(&indio_dev->dev, "channel %d misconfigured\n",	chans[c]);  in stm32_adc_legacy_chan_init()
1959 				return -EINVAL;  in stm32_adc_legacy_chan_init()
1967 	if (adc->nsmps > 0) {  in stm32_adc_legacy_chan_init()
1968 		ret = device_property_read_u32_array(dev, "st,min-sample-time-nsecs",  in stm32_adc_legacy_chan_init()
1969 						     smps, adc->nsmps);  in stm32_adc_legacy_chan_init()
1982 		if (i < adc->nsmps)  in stm32_adc_legacy_chan_init()
2002 				adc->int_ch[i] = chan;  in stm32_adc_populate_int_ch()
2006 			/* Get calibration data for vrefint channel */  in stm32_adc_populate_int_ch()
2007 			ret = nvmem_cell_read_u16(&indio_dev->dev, "vrefint", &vrefint);  in stm32_adc_populate_int_ch()
2008 			if (ret && ret != -ENOENT) {  in stm32_adc_populate_int_ch()
2009 				return dev_err_probe(indio_dev->dev.parent, ret,  in stm32_adc_populate_int_ch()
2012 			if (ret == -ENOENT) {  in stm32_adc_populate_int_ch()
2013 				dev_dbg(&indio_dev->dev, "vrefint calibration not found. Skip vrefint channel\n");  in stm32_adc_populate_int_ch()
2016 				dev_dbg(&indio_dev->dev, "Null vrefint calibration value. Skip vrefint channel\n");  in stm32_adc_populate_int_ch()
2017 				return -ENOENT;  in stm32_adc_populate_int_ch()
2019 			adc->int_ch[i] = chan;  in stm32_adc_populate_int_ch()
2020 			adc->vrefint.vrefint_cal = vrefint;  in stm32_adc_populate_int_ch()
2031 	const struct stm32_adc_info *adc_info = adc->cfg->adc_info;  in stm32_adc_generic_chan_init()
2038 	device_for_each_child_node(&indio_dev->dev, child) {  in stm32_adc_generic_chan_init()
2041 			dev_err(&indio_dev->dev, "Missing channel index %d\n", ret);  in stm32_adc_generic_chan_init()
2049 				dev_err(&indio_dev->dev, "Label %s exceeds %d characters\n",  in stm32_adc_generic_chan_init()
2051 				ret = -EINVAL;  in stm32_adc_generic_chan_init()
2054 			strncpy(adc->chan_name[val], name, STM32_ADC_CH_SZ);  in stm32_adc_generic_chan_init()
2056 			if (ret == -ENOENT)  in stm32_adc_generic_chan_init()
2060 		} else if (ret != -EINVAL) {  in stm32_adc_generic_chan_init()
2061 			dev_err(&indio_dev->dev, "Invalid label %d\n", ret);  in stm32_adc_generic_chan_init()
2065 		if (val >= adc_info->max_channels) {  in stm32_adc_generic_chan_init()
2066 			dev_err(&indio_dev->dev, "Invalid channel %d\n", val);  in stm32_adc_generic_chan_init()
2067 			ret = -EINVAL;  in stm32_adc_generic_chan_init()
2072 		ret = fwnode_property_read_u32_array(child, "diff-channels", vin, 2);  in stm32_adc_generic_chan_init()
2073 		/* diff-channels is optional */  in stm32_adc_generic_chan_init()
2076 			if (vin[0] != val || vin[1] >= adc_info->max_channels) {  in stm32_adc_generic_chan_init()
2077 				dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n",  in stm32_adc_generic_chan_init()
2081 		} else if (ret != -EINVAL) {  in stm32_adc_generic_chan_init()
2082 			dev_err(&indio_dev->dev, "Invalid diff-channels property %d\n", ret);  in stm32_adc_generic_chan_init()
2090 		ret = fwnode_property_read_u32(child, "st,min-sample-time-ns", &val);  in stm32_adc_generic_chan_init()
2091 		/* st,min-sample-time-ns is optional */  in stm32_adc_generic_chan_init()
2092 		if (ret && ret != -EINVAL) {  in stm32_adc_generic_chan_init()
2093 			dev_err(&indio_dev->dev, "Invalid st,min-sample-time-ns property %d\n",  in stm32_adc_generic_chan_init()
2116 	const struct stm32_adc_info *adc_info = adc->cfg->adc_info;  in stm32_adc_chan_fw_init()
2122 		adc->int_ch[i] = STM32_ADC_INT_CH_NONE;  in stm32_adc_chan_fw_init()
2124 	num_channels = device_get_child_node_count(&indio_dev->dev);  in stm32_adc_chan_fw_init()
2131 			dev_err(indio_dev->dev.parent, "No channel found\n");  in stm32_adc_chan_fw_init()
2132 			return -ENODATA;  in stm32_adc_chan_fw_init()
2140 	if (num_channels > adc_info->max_channels) {  in stm32_adc_chan_fw_init()
2141 		dev_err(&indio_dev->dev, "Channel number [%d] exceeds %d\n",  in stm32_adc_chan_fw_init()
2142 			num_channels, adc_info->max_channels);  in stm32_adc_chan_fw_init()
2143 		return -EINVAL;  in stm32_adc_chan_fw_init()
2149 	channels = devm_kcalloc(&indio_dev->dev, num_channels,  in stm32_adc_chan_fw_init()
2152 		return -ENOMEM;  in stm32_adc_chan_fw_init()
2166 		timestamp->type = IIO_TIMESTAMP;  in stm32_adc_chan_fw_init()
2167 		timestamp->channel = -1;  in stm32_adc_chan_fw_init()
2168 		timestamp->scan_index = scan_index;  in stm32_adc_chan_fw_init()
2169 		timestamp->scan_type.sign = 's';  in stm32_adc_chan_fw_init()
2170 		timestamp->scan_type.realbits = 64;  in stm32_adc_chan_fw_init()
2171 		timestamp->scan_type.storagebits = 64;  in stm32_adc_chan_fw_init()
2176 	indio_dev->num_channels = scan_index;  in stm32_adc_chan_fw_init()
2177 	indio_dev->channels = channels;  in stm32_adc_chan_fw_init()
2188 	adc->dma_chan = dma_request_chan(dev, "rx");  in stm32_adc_dma_request()
2189 	if (IS_ERR(adc->dma_chan)) {  in stm32_adc_dma_request()
2190 		ret = PTR_ERR(adc->dma_chan);  in stm32_adc_dma_request()
2191 		if (ret != -ENODEV)  in stm32_adc_dma_request()
2196 		adc->dma_chan = NULL;  in stm32_adc_dma_request()
2200 	adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,  in stm32_adc_dma_request()
2202 					 &adc->rx_dma_buf, GFP_KERNEL);  in stm32_adc_dma_request()
2203 	if (!adc->rx_buf) {  in stm32_adc_dma_request()
2204 		ret = -ENOMEM;  in stm32_adc_dma_request()
2208 	/* Configure DMA channel to read data register */  in stm32_adc_dma_request()
2210 	config.src_addr = (dma_addr_t)adc->common->phys_base;  in stm32_adc_dma_request()
2211 	config.src_addr += adc->offset + adc->cfg->regs->dr;  in stm32_adc_dma_request()
2214 	ret = dmaengine_slave_config(adc->dma_chan, &config);  in stm32_adc_dma_request()
2221 	dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,  in stm32_adc_dma_request()
2222 			  adc->rx_buf, adc->rx_dma_buf);  in stm32_adc_dma_request()
2224 	dma_release_channel(adc->dma_chan);  in stm32_adc_dma_request()
2232 	struct device *dev = &pdev->dev;  in stm32_adc_probe()
2238 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));  in stm32_adc_probe()
2240 		return -ENOMEM;  in stm32_adc_probe()
2243 	adc->common = dev_get_drvdata(pdev->dev.parent);  in stm32_adc_probe()
2244 	spin_lock_init(&adc->lock);  in stm32_adc_probe()
2245 	init_completion(&adc->completion);  in stm32_adc_probe()
2246 	adc->cfg = device_get_match_data(dev);  in stm32_adc_probe()
2248 	indio_dev->name = dev_name(&pdev->dev);  in stm32_adc_probe()
2249 	device_set_node(&indio_dev->dev, dev_fwnode(&pdev->dev));  in stm32_adc_probe()
2250 	indio_dev->info = &stm32_adc_iio_info;  in stm32_adc_probe()
2251 	indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;  in stm32_adc_probe()
2255 	ret = device_property_read_u32(dev, "reg", &adc->offset);  in stm32_adc_probe()
2257 		dev_err(&pdev->dev, "missing reg property\n");  in stm32_adc_probe()
2258 		return -EINVAL;  in stm32_adc_probe()
2261 	adc->irq = platform_get_irq(pdev, 0);  in stm32_adc_probe()
2262 	if (adc->irq < 0)  in stm32_adc_probe()
2263 		return adc->irq;  in stm32_adc_probe()
2265 	ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr,  in stm32_adc_probe()
2267 					0, pdev->name, indio_dev);  in stm32_adc_probe()
2269 		dev_err(&pdev->dev, "failed to request IRQ\n");  in stm32_adc_probe()
2273 	adc->clk = devm_clk_get(&pdev->dev, NULL);  in stm32_adc_probe()
2274 	if (IS_ERR(adc->clk)) {  in stm32_adc_probe()
2275 		ret = PTR_ERR(adc->clk);  in stm32_adc_probe()
2276 		if (ret == -ENOENT && !adc->cfg->clk_required) {  in stm32_adc_probe()
2277 			adc->clk = NULL;  in stm32_adc_probe()
2279 			dev_err(&pdev->dev, "Can't get clock\n");  in stm32_adc_probe()
2292 	if (!adc->dma_chan) {  in stm32_adc_probe()
2309 		dev_err(&pdev->dev, "buffer setup failed\n");  in stm32_adc_probe()
2313 	/* Get stm32-adc-core PM online */  in stm32_adc_probe()
2326 		dev_err(&pdev->dev, "iio dev register failed\n");  in stm32_adc_probe()
2345 	if (adc->dma_chan) {  in stm32_adc_probe()
2346 		dma_free_coherent(adc->dma_chan->device->dev,  in stm32_adc_probe()
2348 				  adc->rx_buf, adc->rx_dma_buf);  in stm32_adc_probe()
2349 		dma_release_channel(adc->dma_chan);  in stm32_adc_probe()
2360 	pm_runtime_get_sync(&pdev->dev);  in stm32_adc_remove()
2362 	stm32_adc_hw_stop(&pdev->dev);  in stm32_adc_remove()
2363 	pm_runtime_disable(&pdev->dev);  in stm32_adc_remove()
2364 	pm_runtime_set_suspended(&pdev->dev);  in stm32_adc_remove()
2365 	pm_runtime_put_noidle(&pdev->dev);  in stm32_adc_remove()
2367 	if (adc->dma_chan) {  in stm32_adc_remove()
2368 		dma_free_coherent(adc->dma_chan->device->dev,  in stm32_adc_remove()
2370 				  adc->rx_buf, adc->rx_dma_buf);  in stm32_adc_remove()
2371 		dma_release_channel(adc->dma_chan);  in stm32_adc_remove()
2400 					 indio_dev->active_scan_mask);  in stm32_adc_resume()
2461 	{ .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2462 	{ .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2463 	{ .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2472 		.name = "stm32-adc",
2482 MODULE_ALIAS("platform:stm32-adc");