Lines Matching full:adc
3 * This file is part of STM32 ADC driver
30 #include "stm32-adc-core.h"
35 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
91 * struct stm32_adc_ic - ADC internal channels
107 * struct stm32_adc_trig_info - ADC trigger info
117 * struct stm32_adc_calib - optional adc calibration data
131 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
143 * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data
200 * @smp_cycles: programmable sampling time (ADC clock cycles)
219 * struct stm32_adc - private data of each ADC IIO instance
220 * @common: reference to ADC block common data
221 * @offset: ADC instance register offset in ADC block
225 * @clk: clock for this adc instance
226 * @irq: interrupt for this adc instance
280 * struct stm32_adc_info - stm32 ADC, per instance config data
390 /* STM32F4 programmable sampling time (ADC clock cycles) */
484 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
523 * STM32 ADC registers access routines
524 * @adc: stm32 adc instance
525 * @reg: reg offset in adc instance
530 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) in stm32_adc_readl() argument
532 return readl_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readl()
535 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
541 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) in stm32_adc_readw() argument
543 return readw_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readw()
546 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) in stm32_adc_writel() argument
548 writel_relaxed(val, adc->common->base + adc->offset + reg); in stm32_adc_writel()
551 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_set_bits() argument
555 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_bits()
556 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); in stm32_adc_set_bits()
557 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_bits()
560 static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_set_bits_common() argument
562 spin_lock(&adc->common->lock); in stm32_adc_set_bits_common()
563 writel_relaxed(readl_relaxed(adc->common->base + reg) | bits, in stm32_adc_set_bits_common()
564 adc->common->base + reg); in stm32_adc_set_bits_common()
565 spin_unlock(&adc->common->lock); in stm32_adc_set_bits_common()
568 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_clr_bits() argument
572 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_clr_bits()
573 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); in stm32_adc_clr_bits()
574 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_clr_bits()
577 static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_clr_bits_common() argument
579 spin_lock(&adc->common->lock); in stm32_adc_clr_bits_common()
580 writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits, in stm32_adc_clr_bits_common()
581 adc->common->base + reg); in stm32_adc_clr_bits_common()
582 spin_unlock(&adc->common->lock); in stm32_adc_clr_bits_common()
587 * @adc: stm32 adc instance
589 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) in stm32_adc_conv_irq_enable() argument
591 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_enable()
592 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_enable()
597 * @adc: stm32 adc instance
599 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) in stm32_adc_conv_irq_disable() argument
601 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_disable()
602 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_disable()
605 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) in stm32_adc_ovr_irq_enable() argument
607 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_enable()
608 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_enable()
611 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) in stm32_adc_ovr_irq_disable() argument
613 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_disable()
614 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_disable()
617 static void stm32_adc_set_res(struct stm32_adc *adc) in stm32_adc_set_res() argument
619 const struct stm32_adc_regs *res = &adc->cfg->regs->res; in stm32_adc_set_res()
622 val = stm32_adc_readl(adc, res->reg); in stm32_adc_set_res()
623 val = (val & ~res->mask) | (adc->res << res->shift); in stm32_adc_set_res()
624 stm32_adc_writel(adc, res->reg, val); in stm32_adc_set_res()
630 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_hw_stop() local
632 if (adc->cfg->unprepare) in stm32_adc_hw_stop()
633 adc->cfg->unprepare(indio_dev); in stm32_adc_hw_stop()
635 clk_disable_unprepare(adc->clk); in stm32_adc_hw_stop()
643 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_hw_start() local
646 ret = clk_prepare_enable(adc->clk); in stm32_adc_hw_start()
650 stm32_adc_set_res(adc); in stm32_adc_hw_start()
652 if (adc->cfg->prepare) { in stm32_adc_hw_start()
653 ret = adc->cfg->prepare(indio_dev); in stm32_adc_hw_start()
661 clk_disable_unprepare(adc->clk); in stm32_adc_hw_start()
668 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_int_ch_enable() local
672 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) in stm32_adc_int_ch_enable()
678 stm32_adc_set_bits(adc, adc->cfg->regs->or_vdd.reg, in stm32_adc_int_ch_enable()
679 adc->cfg->regs->or_vdd.mask); in stm32_adc_int_ch_enable()
683 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg, in stm32_adc_int_ch_enable()
684 adc->cfg->regs->ccr_vref.mask); in stm32_adc_int_ch_enable()
688 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, in stm32_adc_int_ch_enable()
689 adc->cfg->regs->ccr_vbat.mask); in stm32_adc_int_ch_enable()
695 static void stm32_adc_int_ch_disable(struct stm32_adc *adc) in stm32_adc_int_ch_disable() argument
700 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) in stm32_adc_int_ch_disable()
705 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vdd.reg, in stm32_adc_int_ch_disable()
706 adc->cfg->regs->or_vdd.mask); in stm32_adc_int_ch_disable()
709 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg, in stm32_adc_int_ch_disable()
710 adc->cfg->regs->ccr_vref.mask); in stm32_adc_int_ch_disable()
713 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, in stm32_adc_int_ch_disable()
714 adc->cfg->regs->ccr_vbat.mask); in stm32_adc_int_ch_disable()
727 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
732 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_start_conv() local
734 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); in stm32f4_adc_start_conv()
737 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, in stm32f4_adc_start_conv()
740 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); in stm32f4_adc_start_conv()
746 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) in stm32f4_adc_start_conv()
747 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); in stm32f4_adc_start_conv()
752 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_stop_conv() local
754 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); in stm32f4_adc_stop_conv()
755 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); in stm32f4_adc_stop_conv()
757 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); in stm32f4_adc_stop_conv()
758 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, in stm32f4_adc_stop_conv()
764 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_irq_clear() local
766 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32f4_adc_irq_clear()
771 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_start_conv() local
781 spin_lock_irqsave(&adc->lock, flags); in stm32h7_adc_start_conv()
782 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); in stm32h7_adc_start_conv()
784 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); in stm32h7_adc_start_conv()
785 spin_unlock_irqrestore(&adc->lock, flags); in stm32h7_adc_start_conv()
787 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); in stm32h7_adc_start_conv()
792 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_stop_conv() local
796 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); in stm32h7_adc_stop_conv()
804 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); in stm32h7_adc_stop_conv()
809 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_irq_clear() local
811 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32h7_adc_irq_clear()
816 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_exit_pwr_down() local
820 /* Exit deep power down, then enable ADC voltage regulator */ in stm32h7_adc_exit_pwr_down()
821 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_exit_pwr_down()
822 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); in stm32h7_adc_exit_pwr_down()
824 if (adc->common->rate > STM32H7_BOOST_CLKRATE) in stm32h7_adc_exit_pwr_down()
825 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); in stm32h7_adc_exit_pwr_down()
828 if (!adc->cfg->has_vregready) { in stm32h7_adc_exit_pwr_down()
837 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_exit_pwr_down()
844 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) in stm32h7_adc_enter_pwr_down() argument
846 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); in stm32h7_adc_enter_pwr_down()
848 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ in stm32h7_adc_enter_pwr_down()
849 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_enter_pwr_down()
854 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_enable() local
858 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); in stm32h7_adc_enable()
860 /* Poll for ADRDY to be set (after adc startup time) */ in stm32h7_adc_enable()
865 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); in stm32h7_adc_enable()
866 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); in stm32h7_adc_enable()
869 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); in stm32h7_adc_enable()
877 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_disable() local
881 if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) in stm32h7_adc_disable()
884 /* Disable ADC and wait until it's effectively disabled */ in stm32h7_adc_disable()
885 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); in stm32h7_adc_disable()
896 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable
900 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_read_selfcalib() local
908 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_read_selfcalib()
919 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); in stm32h7_adc_read_selfcalib()
920 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); in stm32h7_adc_read_selfcalib()
921 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_read_selfcalib()
927 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT); in stm32h7_adc_read_selfcalib()
928 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); in stm32h7_adc_read_selfcalib()
929 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; in stm32h7_adc_read_selfcalib()
930 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); in stm32h7_adc_read_selfcalib()
931 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; in stm32h7_adc_read_selfcalib()
932 adc->cal.calibrated = true; in stm32h7_adc_read_selfcalib()
940 * Note: ADC must be enabled, with no on-going conversions.
944 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_restore_selfcalib() local
948 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | in stm32h7_adc_restore_selfcalib()
949 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); in stm32h7_adc_restore_selfcalib()
950 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val); in stm32h7_adc_restore_selfcalib()
959 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_restore_selfcalib()
960 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); in stm32h7_adc_restore_selfcalib()
961 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_restore_selfcalib()
977 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_restore_selfcalib()
985 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); in stm32h7_adc_restore_selfcalib()
986 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { in stm32h7_adc_restore_selfcalib()
998 * Fixed timeout value for ADC calibration.
1003 * - 131,072 ADC clock cycle for the linear calibration
1004 * - 20 ADC clock cycle for the offset calibration
1011 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
1013 * Note: Must be called once ADC is out of power down.
1017 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_selfcalib() local
1021 if (adc->cal.calibrated) in stm32h7_adc_selfcalib()
1024 /* ADC must be disabled for calibration */ in stm32h7_adc_selfcalib()
1032 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF); in stm32h7_adc_selfcalib()
1033 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN); in stm32h7_adc_selfcalib()
1036 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); in stm32h7_adc_selfcalib()
1051 stm32_adc_set_bits(adc, STM32H7_ADC_CR, in stm32h7_adc_selfcalib()
1053 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); in stm32h7_adc_selfcalib()
1063 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, in stm32h7_adc_selfcalib()
1070 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
1073 * Configure channels as single ended or differential before enabling ADC.
1074 * Enable ADC.
1082 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_prepare() local
1096 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); in stm32h7_adc_prepare()
1110 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); in stm32h7_adc_prepare()
1117 stm32_adc_int_ch_disable(adc); in stm32h7_adc_prepare()
1119 stm32h7_adc_enter_pwr_down(adc); in stm32h7_adc_prepare()
1126 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_unprepare() local
1128 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); in stm32h7_adc_unprepare()
1130 stm32_adc_int_ch_disable(adc); in stm32h7_adc_unprepare()
1131 stm32h7_adc_enter_pwr_down(adc); in stm32h7_adc_unprepare()
1141 * Configure ADC scan sequence based on selected channels in scan_mask.
1148 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_conf_scan_seq() local
1149 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; in stm32_adc_conf_scan_seq()
1155 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); in stm32_adc_conf_scan_seq()
1156 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); in stm32_adc_conf_scan_seq()
1171 val = stm32_adc_readl(adc, sqr[i].reg); in stm32_adc_conf_scan_seq()
1174 stm32_adc_writel(adc, sqr[i].reg, val); in stm32_adc_conf_scan_seq()
1181 val = stm32_adc_readl(adc, sqr[0].reg); in stm32_adc_conf_scan_seq()
1184 stm32_adc_writel(adc, sqr[0].reg, val); in stm32_adc_conf_scan_seq()
1199 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_get_trig_extsel() local
1203 for (i = 0; adc->cfg->trigs[i].name; i++) { in stm32_adc_get_trig_extsel()
1210 !strcmp(adc->cfg->trigs[i].name, trig->name)) { in stm32_adc_get_trig_extsel()
1211 return adc->cfg->trigs[i].extsel; in stm32_adc_get_trig_extsel()
1230 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_trig() local
1242 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; in stm32_adc_set_trig()
1245 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_trig()
1246 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); in stm32_adc_set_trig()
1247 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); in stm32_adc_set_trig()
1248 val |= exten << adc->cfg->regs->exten.shift; in stm32_adc_set_trig()
1249 val |= extsel << adc->cfg->regs->extsel.shift; in stm32_adc_set_trig()
1250 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); in stm32_adc_set_trig()
1251 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_trig()
1260 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_trig_pol() local
1262 adc->trigger_polarity = type; in stm32_adc_set_trig_pol()
1270 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_get_trig_pol() local
1272 return adc->trigger_polarity; in stm32_adc_get_trig_pol()
1302 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_single_conv() local
1304 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_single_conv()
1309 reinit_completion(&adc->completion); in stm32_adc_single_conv()
1311 adc->bufi = 0; in stm32_adc_single_conv()
1318 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); in stm32_adc_single_conv()
1319 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); in stm32_adc_single_conv()
1322 val = stm32_adc_readl(adc, regs->sqr[1].reg); in stm32_adc_single_conv()
1325 stm32_adc_writel(adc, regs->sqr[1].reg, val); in stm32_adc_single_conv()
1328 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); in stm32_adc_single_conv()
1331 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); in stm32_adc_single_conv()
1333 stm32_adc_conv_irq_enable(adc); in stm32_adc_single_conv()
1335 adc->cfg->start_conv(indio_dev, false); in stm32_adc_single_conv()
1338 &adc->completion, STM32_ADC_TIMEOUT); in stm32_adc_single_conv()
1344 *res = adc->buffer[0]; in stm32_adc_single_conv()
1348 adc->cfg->stop_conv(indio_dev); in stm32_adc_single_conv()
1350 stm32_adc_conv_irq_disable(adc); in stm32_adc_single_conv()
1362 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_read_raw() local
1377 *val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val; in stm32_adc_read_raw()
1384 *val = adc->common->vref_mv * 2; in stm32_adc_read_raw()
1387 *val = adc->common->vref_mv; in stm32_adc_read_raw()
1407 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_irq_clear() local
1409 adc->cfg->irq_clear(indio_dev, msk); in stm32_adc_irq_clear()
1415 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_threaded_isr() local
1416 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_threaded_isr()
1417 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_threaded_isr()
1423 * This requires to stop ADC first. OVR bit state in ISR, in stm32_adc_threaded_isr()
1426 adc->cfg->stop_conv(indio_dev); in stm32_adc_threaded_isr()
1438 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_isr() local
1439 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_isr()
1440 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_isr()
1450 stm32_adc_ovr_irq_disable(adc); in stm32_adc_isr()
1451 stm32_adc_conv_irq_disable(adc); in stm32_adc_isr()
1457 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); in stm32_adc_isr()
1459 adc->bufi++; in stm32_adc_isr()
1460 if (adc->bufi >= adc->num_conv) { in stm32_adc_isr()
1461 stm32_adc_conv_irq_disable(adc); in stm32_adc_isr()
1465 complete(&adc->completion); in stm32_adc_isr()
1474 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1478 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1489 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_watermark() local
1500 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); in stm32_adc_set_watermark()
1508 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_update_scan_mode() local
1516 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); in stm32_adc_update_scan_mode()
1544 * To read a value from an ADC register:
1545 * echo [ADC reg offset] > direct_reg_access
1548 * To write a value in a ADC register:
1555 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_debugfs_reg_access() local
1564 stm32_adc_writel(adc, reg, writeval); in stm32_adc_debugfs_reg_access()
1566 *readval = stm32_adc_readl(adc, reg); in stm32_adc_debugfs_reg_access()
1583 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) in stm32_adc_dma_residue() argument
1588 status = dmaengine_tx_status(adc->dma_chan, in stm32_adc_dma_residue()
1589 adc->dma_chan->cookie, in stm32_adc_dma_residue()
1593 unsigned int i = adc->rx_buf_sz - state.residue; in stm32_adc_dma_residue()
1597 if (i >= adc->bufi) in stm32_adc_dma_residue()
1598 size = i - adc->bufi; in stm32_adc_dma_residue()
1600 size = adc->rx_buf_sz + i - adc->bufi; in stm32_adc_dma_residue()
1611 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_buffer_done() local
1612 int residue = stm32_adc_dma_residue(adc); in stm32_adc_dma_buffer_done()
1623 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_dma_buffer_done()
1626 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; in stm32_adc_dma_buffer_done()
1631 adc->bufi += indio_dev->scan_bytes; in stm32_adc_dma_buffer_done()
1632 if (adc->bufi >= adc->rx_buf_sz) in stm32_adc_dma_buffer_done()
1633 adc->bufi = 0; in stm32_adc_dma_buffer_done()
1639 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_start() local
1644 if (!adc->dma_chan) in stm32_adc_dma_start()
1648 adc->rx_buf_sz, adc->rx_buf_sz / 2); in stm32_adc_dma_start()
1651 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, in stm32_adc_dma_start()
1652 adc->rx_dma_buf, in stm32_adc_dma_start()
1653 adc->rx_buf_sz, adc->rx_buf_sz / 2, in stm32_adc_dma_start()
1665 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_dma_start()
1670 dma_async_issue_pending(adc->dma_chan); in stm32_adc_dma_start()
1677 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_buffer_postenable() local
1697 /* Reset adc buffer index */ in stm32_adc_buffer_postenable()
1698 adc->bufi = 0; in stm32_adc_buffer_postenable()
1700 stm32_adc_ovr_irq_enable(adc); in stm32_adc_buffer_postenable()
1702 if (!adc->dma_chan) in stm32_adc_buffer_postenable()
1703 stm32_adc_conv_irq_enable(adc); in stm32_adc_buffer_postenable()
1705 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); in stm32_adc_buffer_postenable()
1720 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_buffer_predisable() local
1723 adc->cfg->stop_conv(indio_dev); in stm32_adc_buffer_predisable()
1724 if (!adc->dma_chan) in stm32_adc_buffer_predisable()
1725 stm32_adc_conv_irq_disable(adc); in stm32_adc_buffer_predisable()
1727 stm32_adc_ovr_irq_disable(adc); in stm32_adc_buffer_predisable()
1729 if (adc->dma_chan) in stm32_adc_buffer_predisable()
1730 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_buffer_predisable()
1750 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_trigger_handler() local
1752 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_trigger_handler()
1755 adc->bufi = 0; in stm32_adc_trigger_handler()
1756 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, in stm32_adc_trigger_handler()
1761 stm32_adc_conv_irq_enable(adc); in stm32_adc_trigger_handler()
1780 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_fw_get_resolution() local
1785 res = adc->cfg->adc_info->resolutions[0]; in stm32_adc_fw_get_resolution()
1787 for (i = 0; i < adc->cfg->adc_info->num_res; i++) in stm32_adc_fw_get_resolution()
1788 if (res == adc->cfg->adc_info->resolutions[i]) in stm32_adc_fw_get_resolution()
1790 if (i >= adc->cfg->adc_info->num_res) { in stm32_adc_fw_get_resolution()
1796 adc->res = i; in stm32_adc_fw_get_resolution()
1801 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) in stm32_adc_smpr_init() argument
1803 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; in stm32_adc_smpr_init()
1811 if (channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) in stm32_adc_smpr_init()
1812 smp_ns = max(smp_ns, adc->cfg->ts_vrefint_ns); in stm32_adc_smpr_init()
1814 /* Determine sampling time (ADC clock cycles) */ in stm32_adc_smpr_init()
1815 period_ns = NSEC_PER_SEC / adc->common->rate; in stm32_adc_smpr_init()
1817 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) in stm32_adc_smpr_init()
1823 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); in stm32_adc_smpr_init()
1830 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_chan_init_one() local
1831 char *name = adc->chan_name[vinp]; in stm32_adc_chan_init_one()
1845 if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) in stm32_adc_chan_init_one()
1852 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; in stm32_adc_chan_init_one()
1857 adc->pcsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
1860 adc->difsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
1862 adc->pcsel |= BIT(chan->channel2); in stm32_adc_chan_init_one()
1866 static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc) in stm32_adc_get_legacy_chan_count() argument
1869 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_get_legacy_chan_count()
1872 ret = device_property_count_u32(dev, "st,adc-channels"); in stm32_adc_get_legacy_chan_count()
1874 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); in stm32_adc_get_legacy_chan_count()
1881 * each st,adc-diff-channels is a group of 2 u32 so we divide @ret in stm32_adc_get_legacy_chan_count()
1884 ret = device_property_count_u32(dev, "st,adc-diff-channels"); in stm32_adc_get_legacy_chan_count()
1890 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); in stm32_adc_get_legacy_chan_count()
1893 adc->num_diff = ret; in stm32_adc_get_legacy_chan_count()
1898 adc->nsmps = device_property_count_u32(dev, "st,min-sample-time-nsecs"); in stm32_adc_get_legacy_chan_count()
1899 if (adc->nsmps > 1 && adc->nsmps != num_channels) { in stm32_adc_get_legacy_chan_count()
1908 struct stm32_adc *adc, in stm32_adc_legacy_chan_init() argument
1912 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_legacy_chan_init()
1915 u32 num_diff = adc->num_diff; in stm32_adc_legacy_chan_init()
1921 ret = device_property_read_u32_array(dev, "st,adc-diff-channels", in stm32_adc_legacy_chan_init()
1943 ret = device_property_read_u32_array(dev, "st,adc-channels", chans, in stm32_adc_legacy_chan_init()
1967 if (adc->nsmps > 0) { in stm32_adc_legacy_chan_init()
1969 smps, adc->nsmps); in stm32_adc_legacy_chan_init()
1982 if (i < adc->nsmps) in stm32_adc_legacy_chan_init()
1986 stm32_adc_smpr_init(adc, channels[i].channel, smp); in stm32_adc_legacy_chan_init()
1995 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_populate_int_ch() local
2002 adc->int_ch[i] = chan; in stm32_adc_populate_int_ch()
2019 adc->int_ch[i] = chan; in stm32_adc_populate_int_ch()
2020 adc->vrefint.vrefint_cal = vrefint; in stm32_adc_populate_int_ch()
2028 struct stm32_adc *adc, in stm32_adc_generic_chan_init() argument
2031 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_generic_chan_init()
2054 strncpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); in stm32_adc_generic_chan_init()
2098 stm32_adc_smpr_init(adc, channels[scan_index].channel, val); in stm32_adc_generic_chan_init()
2100 stm32_adc_smpr_init(adc, vin[1], val); in stm32_adc_generic_chan_init()
2115 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_chan_fw_init() local
2116 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_chan_fw_init()
2122 adc->int_ch[i] = STM32_ADC_INT_CH_NONE; in stm32_adc_chan_fw_init()
2129 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc); in stm32_adc_chan_fw_init()
2155 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels, in stm32_adc_chan_fw_init()
2158 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels); in stm32_adc_chan_fw_init()
2184 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_request() local
2188 adc->dma_chan = dma_request_chan(dev, "rx"); in stm32_adc_dma_request()
2189 if (IS_ERR(adc->dma_chan)) { in stm32_adc_dma_request()
2190 ret = PTR_ERR(adc->dma_chan); in stm32_adc_dma_request()
2196 adc->dma_chan = NULL; in stm32_adc_dma_request()
2200 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, in stm32_adc_dma_request()
2202 &adc->rx_dma_buf, GFP_KERNEL); in stm32_adc_dma_request()
2203 if (!adc->rx_buf) { in stm32_adc_dma_request()
2210 config.src_addr = (dma_addr_t)adc->common->phys_base; in stm32_adc_dma_request()
2211 config.src_addr += adc->offset + adc->cfg->regs->dr; in stm32_adc_dma_request()
2214 ret = dmaengine_slave_config(adc->dma_chan, &config); in stm32_adc_dma_request()
2221 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, in stm32_adc_dma_request()
2222 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_dma_request()
2224 dma_release_channel(adc->dma_chan); in stm32_adc_dma_request()
2234 struct stm32_adc *adc; in stm32_adc_probe() local
2238 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); in stm32_adc_probe()
2242 adc = iio_priv(indio_dev); in stm32_adc_probe()
2243 adc->common = dev_get_drvdata(pdev->dev.parent); in stm32_adc_probe()
2244 spin_lock_init(&adc->lock); in stm32_adc_probe()
2245 init_completion(&adc->completion); in stm32_adc_probe()
2246 adc->cfg = device_get_match_data(dev); in stm32_adc_probe()
2255 ret = device_property_read_u32(dev, "reg", &adc->offset); in stm32_adc_probe()
2261 adc->irq = platform_get_irq(pdev, 0); in stm32_adc_probe()
2262 if (adc->irq < 0) in stm32_adc_probe()
2263 return adc->irq; in stm32_adc_probe()
2265 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, in stm32_adc_probe()
2273 adc->clk = devm_clk_get(&pdev->dev, NULL); in stm32_adc_probe()
2274 if (IS_ERR(adc->clk)) { in stm32_adc_probe()
2275 ret = PTR_ERR(adc->clk); in stm32_adc_probe()
2276 if (ret == -ENOENT && !adc->cfg->clk_required) { in stm32_adc_probe()
2277 adc->clk = NULL; in stm32_adc_probe()
2292 if (!adc->dma_chan) { in stm32_adc_probe()
2313 /* Get stm32-adc-core PM online */ in stm32_adc_probe()
2345 if (adc->dma_chan) { in stm32_adc_probe()
2346 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_probe()
2348 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_probe()
2349 dma_release_channel(adc->dma_chan); in stm32_adc_probe()
2358 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_remove() local
2367 if (adc->dma_chan) { in stm32_adc_remove()
2368 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_remove()
2370 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_remove()
2371 dma_release_channel(adc->dma_chan); in stm32_adc_remove()
2461 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2462 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2463 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2472 .name = "stm32-adc",
2480 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
2482 MODULE_ALIAS("platform:stm32-adc");