1 // SPDX-License-Identifier: GPL-2.0-only
30  * HR Timers-based version loads CPU only up to 10% during back to back ADC
31  * conversion, while busy wait-based version consumes whole CPU power.
88 		mutex_lock(&priv->lock);  in ep93xx_read_raw()
89 		if (priv->lastch != channel->channel) {  in ep93xx_read_raw()
90 			priv->lastch = channel->channel;  in ep93xx_read_raw()
92 			 * Switch register is software-locked, unlocking must be  in ep93xx_read_raw()
96 			writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK);  in ep93xx_read_raw()
97 			writel_relaxed(channel->address,  in ep93xx_read_raw()
98 				       priv->base + EP93XX_ADC_SWITCH);  in ep93xx_read_raw()
101 			 * Settling delay depends on module clock and could be  in ep93xx_read_raw()
102 			 * 2ms or 500us  in ep93xx_read_raw()
107 		readl_relaxed(priv->base + EP93XX_ADC_RESULT);  in ep93xx_read_raw()
117 			t = readl_relaxed(priv->base + EP93XX_ADC_RESULT);  in ep93xx_read_raw()
124 				dev_err(&iiodev->dev, "Conversion timeout\n");  in ep93xx_read_raw()
125 				ret = -ETIMEDOUT;  in ep93xx_read_raw()
131 		mutex_unlock(&priv->lock);  in ep93xx_read_raw()
135 		/* According to datasheet, range is -25000..25000 */  in ep93xx_read_raw()
146 	return -EINVAL;  in ep93xx_read_raw()
160 	iiodev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));  in ep93xx_adc_probe()
162 		return -ENOMEM;  in ep93xx_adc_probe()
165 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in ep93xx_adc_probe()
166 	if (IS_ERR(priv->base))  in ep93xx_adc_probe()
167 		return PTR_ERR(priv->base);  in ep93xx_adc_probe()
169 	iiodev->name = dev_name(&pdev->dev);  in ep93xx_adc_probe()
170 	iiodev->modes = INDIO_DIRECT_MODE;  in ep93xx_adc_probe()
171 	iiodev->info = &ep93xx_adc_info;  in ep93xx_adc_probe()
172 	iiodev->num_channels = ARRAY_SIZE(ep93xx_adc_channels);  in ep93xx_adc_probe()
173 	iiodev->channels = ep93xx_adc_channels;  in ep93xx_adc_probe()
175 	priv->lastch = -1;  in ep93xx_adc_probe()
176 	mutex_init(&priv->lock);  in ep93xx_adc_probe()
180 	priv->clk = devm_clk_get(&pdev->dev, NULL);  in ep93xx_adc_probe()
181 	if (IS_ERR(priv->clk)) {  in ep93xx_adc_probe()
182 		dev_err(&pdev->dev, "Cannot obtain clock\n");  in ep93xx_adc_probe()
183 		return PTR_ERR(priv->clk);  in ep93xx_adc_probe()
186 	pclk = clk_get_parent(priv->clk);  in ep93xx_adc_probe()
188 		dev_warn(&pdev->dev, "Cannot obtain parent clock\n");  in ep93xx_adc_probe()
192 		 * EP93xx ADC supports two clock divisors -- 4 and 16,  in ep93xx_adc_probe()
194 		 * with 500us or 2ms settling time respectively.  in ep93xx_adc_probe()
197 		ret = clk_set_rate(priv->clk, clk_get_rate(pclk) / 16);  in ep93xx_adc_probe()
199 			dev_warn(&pdev->dev, "Cannot set clock rate\n");  in ep93xx_adc_probe()
206 	ret = clk_prepare_enable(priv->clk);  in ep93xx_adc_probe()
208 		dev_err(&pdev->dev, "Cannot enable clock\n");  in ep93xx_adc_probe()
214 		clk_disable_unprepare(priv->clk);  in ep93xx_adc_probe()
225 	clk_disable_unprepare(priv->clk);  in ep93xx_adc_remove()
232 		.name = "ep93xx-adc",
242 MODULE_ALIAS("platform:ep93xx-adc");