432 #define at91_adc_writel(st, reg, val)					\  macro
799 		at91_adc_writel(st, COR, cur_cor | cor);  in at91_adc_cor()
801 		at91_adc_writel(st, COR, cur_cor & ~cor);  in at91_adc_cor()
831 		at91_adc_writel(st, IDR, BIT(channel));  in at91_adc_eoc_dis()
837 		at91_adc_writel(st, IER, BIT(channel));  in at91_adc_eoc_ena()
839 		at91_adc_writel(st, EOC_IER, BIT(channel));  in at91_adc_eoc_ena()
893 	at91_adc_writel(st, EMR, emr);  in at91_adc_config_emr()
966 		at91_adc_writel(st, IDR,  in at91_adc_configure_touch()
968 		at91_adc_writel(st, TSMR, 0);  in at91_adc_configure_touch()
997 	at91_adc_writel(st, TSMR, tsmr);  in at91_adc_configure_touch()
1002 	at91_adc_writel(st, ACR, acr);  in at91_adc_configure_touch()
1009 	at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);  in at91_adc_configure_touch()
1124 	at91_adc_writel(st, TRGR, status);  in at91_adc_configure_trigger_registers()
1256 	at91_adc_writel(st, IER, AT91_SAMA5D2_IER_GOVRE);  in at91_adc_dma_start()
1328 		at91_adc_writel(st, CHER, BIT(chan->channel));  in at91_adc_buffer_prepare()
1332 		at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY);  in at91_adc_buffer_prepare()
1377 		at91_adc_writel(st, CHDR, BIT(chan->channel));  in at91_adc_buffer_postdisable()
1384 		at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_DRDY);  in at91_adc_buffer_postdisable()
1542 		at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);  in at91_adc_trigger_handler()
1600 	at91_adc_writel(st, MR, mr);  in at91_adc_setup_samp_freq()
1649 	at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN);  in at91_adc_pen_detect_interrupt()
1650 	at91_adc_writel(st, IER, AT91_SAMA5D2_IER_NOPEN |  in at91_adc_pen_detect_interrupt()
1653 	at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |  in at91_adc_pen_detect_interrupt()
1662 	at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);  in at91_adc_no_pen_detect_interrupt()
1663 	at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_NOPEN |  in at91_adc_no_pen_detect_interrupt()
1670 	at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);  in at91_adc_no_pen_detect_interrupt()
1773 	at91_adc_writel(st, CHER, BIT(chan->channel));  in at91_adc_read_info_raw()
1780 		at91_adc_writel(st, TEMPMR, AT91_SAMA5D2_TEMPMR_TEMPON);  in at91_adc_read_info_raw()
1782 	at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);  in at91_adc_read_info_raw()
1801 		at91_adc_writel(st, TEMPMR, 0U);  in at91_adc_read_info_raw()
1802 	at91_adc_writel(st, CHDR, BIT(chan->channel));  in at91_adc_read_info_raw()
1888 	at91_adc_writel(st, ACR, tmp);  in at91_adc_read_temp()
1895 	at91_adc_writel(st, ACR, tmp);  in at91_adc_read_temp()
2160 	at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);  in at91_adc_hw_init()
2162 		at91_adc_writel(st, EOC_IDR, 0xffffffff);  in at91_adc_hw_init()
2163 	at91_adc_writel(st, IDR, 0xffffffff);  in at91_adc_hw_init()
2168 	at91_adc_writel(st, MR,  in at91_adc_hw_init()
2544 	at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);  in at91_adc_suspend()