Lines Matching +full:4 +full:- +full:ch
1 // SPDX-License-Identifier: GPL-2.0
19 #define AD7616_OS_MASK GENMASK(4, 2)
26 * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register.
27 * For channels from second group(8-15) the order is the same, only with
30 #define AD7616_RANGE_CH_ADDR(ch) ((ch) >> 2) argument
32 #define AD7616_RANGE_CH_MSK(ch) (0b11 << (((ch) & 0b11) * 2)) argument
33 #define AD7616_RANGE_CH_MODE(ch, mode) ((mode) << ((((ch) & 0b11)) * 2)) argument
40 * Each register stores range for 2 channels(4 bits per channel).
42 #define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) & 0x1))) argument
43 #define AD7606_RANGE_CH_MODE(ch, mode) \ argument
44 ((GENMASK(3, 0) & mode) << (4 * ((ch) & 0x1)))
45 #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) argument
54 AD7616_CHANNEL(4),
74 AD7616_CHANNEL(4),
81 1, 2, 4, 8, 16, 32, 64, 128, 256
113 dev_err(&spi->dev, "SPI read error\n"); in ad7606_spi_read_block()
125 struct spi_device *spi = to_spi_device(st->dev); in ad7606_spi_reg_read()
128 .tx_buf = &st->d16[0], in ad7606_spi_reg_read()
132 .rx_buf = &st->d16[1], in ad7606_spi_reg_read()
138 st->d16[0] = cpu_to_be16(st->bops->rd_wr_cmd(addr, 0) << 8); in ad7606_spi_reg_read()
144 return be16_to_cpu(st->d16[1]); in ad7606_spi_reg_read()
151 struct spi_device *spi = to_spi_device(st->dev); in ad7606_spi_reg_write()
153 st->d16[0] = cpu_to_be16((st->bops->rd_wr_cmd(addr, 1) << 8) | in ad7606_spi_reg_write()
156 return spi_write(spi, &st->d16[0], sizeof(st->d16[0])); in ad7606_spi_reg_write()
166 readval = st->bops->reg_read(st, addr); in ad7606_spi_write_mask()
173 return st->bops->reg_write(st, addr, readval); in ad7606_spi_write_mask()
176 static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int val) in ad7616_write_scale_sw() argument
184 * The range of channels from A are stored in registers with address 4 in ad7616_write_scale_sw()
189 ch_index = ch >> 1; in ad7616_write_scale_sw()
193 if ((ch & 0x1) == 0) /* channel A */ in ad7616_write_scale_sw()
200 return st->bops->write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index), in ad7616_write_scale_sw()
208 return st->bops->write_mask(st, AD7616_CONFIGURATION_REGISTER, in ad7616_write_os_sw()
212 static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int val) in ad7606_write_scale_sw() argument
217 AD7606_RANGE_CH_ADDR(ch), in ad7606_write_scale_sw()
218 AD7606_RANGE_CH_MSK(ch), in ad7606_write_scale_sw()
219 AD7606_RANGE_CH_MODE(ch, val)); in ad7606_write_scale_sw()
237 indio_dev->channels = ad7616_sw_channels; in ad7616_sw_mode_config()
239 st->write_scale = ad7616_write_scale_sw; in ad7616_sw_mode_config()
240 st->write_os = &ad7616_write_os_sw; in ad7616_sw_mode_config()
243 return st->bops->write_mask(st, in ad7616_sw_mode_config()
260 if (st->gpio_os) { in ad7606B_sw_mode_config()
262 st->gpio_os->desc, st->gpio_os->info, os); in ad7606B_sw_mode_config()
265 st->oversampling_avail = ad7606B_oversampling_avail; in ad7606B_sw_mode_config()
266 st->num_os_ratios = ARRAY_SIZE(ad7606B_oversampling_avail); in ad7606B_sw_mode_config()
268 st->write_scale = ad7606_write_scale_sw; in ad7606B_sw_mode_config()
269 st->write_os = &ad7606_write_os_sw; in ad7606B_sw_mode_config()
272 st->bops->reg_write(st, in ad7606B_sw_mode_config()
280 indio_dev->channels = ad7606b_sw_channels; in ad7606B_sw_mode_config()
312 switch (id->driver_data) { in ad7606_spi_probe()
324 return ad7606_probe(&spi->dev, spi->irq, NULL, in ad7606_spi_probe()
325 id->name, id->driver_data, in ad7606_spi_probe()
330 { "ad7605-4", ID_AD7605_4 },
331 { "ad7606-4", ID_AD7606_4 },
332 { "ad7606-6", ID_AD7606_6 },
333 { "ad7606-8", ID_AD7606_8 },
341 { .compatible = "adi,ad7605-4" },
342 { .compatible = "adi,ad7606-4" },
343 { .compatible = "adi,ad7606-6" },
344 { .compatible = "adi,ad7606-8" },