Lines Matching full:d7
63 #define AD7280A_CTRL_LB_REG 0xE /* D7 to D0, Read/write */
76 #define AD7280A_CELL_OVERVOLTAGE_REG 0xF /* D7 to D0, Read/write */
77 #define AD7280A_CELL_UNDERVOLTAGE_REG 0x10 /* D7 to D0, Read/write */
78 #define AD7280A_AUX_ADC_OVERVOLTAGE_REG 0x11 /* D7 to D0, Read/write */
79 #define AD7280A_AUX_ADC_UNDERVOLTAGE_REG 0x12 /* D7 to D0, Read/write */
81 #define AD7280A_ALERT_REG 0x13 /* D7 to D0, Read/write */
90 #define AD7280A_CELL_BALANCE_REG 0x14 /* D7 to D0, Read/write */
92 #define AD7280A_CB1_TIMER_REG 0x15 /* D7 to D0, Read/write */
94 #define AD7280A_CB2_TIMER_REG 0x16 /* D7 to D0, Read/write */
95 #define AD7280A_CB3_TIMER_REG 0x17 /* D7 to D0, Read/write */
96 #define AD7280A_CB4_TIMER_REG 0x18 /* D7 to D0, Read/write */
97 #define AD7280A_CB5_TIMER_REG 0x19 /* D7 to D0, Read/write */
98 #define AD7280A_CB6_TIMER_REG 0x1A /* D7 to D0, Read/write */
99 #define AD7280A_PD_TIMER_REG 0x1B /* D7 to D0, Read/write */
100 #define AD7280A_READ_REG 0x1C /* D7 to D0, Read/write */
102 #define AD7280A_CNVST_CTRL_REG 0x1D /* D7 to D0, Read/write */