32 #define AD7192_REG_MODE		1 /* Mode Register	     (RW, 24-bit */
55 #define AD7192_STAT_CH2		BIT(1) /* Channel 2 */
56 #define AD7192_STAT_CH1		BIT(0) /* Channel 1 */
74 #define AD7192_MODE_SINGLE		1 /* Single Conversion Mode */
85 #define AD7192_CLK_EXT_MCLK2		1 /* External Clock applied to MCLK2 */
104 #define AD7192_CH_AIN3P_AIN4M	BIT(1) /* AIN3(+) - AIN4(-) */
141 #define AD7192_GPOCON_P1DAT	BIT(1) /* P1 state */
148 #define AD7192_NO_SYNC_FILTER	1
205 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_set_syscalib_mode()  local
207 	st->syscalib_mode[chan->channel] = mode;  in ad7192_set_syscalib_mode()
215 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_get_syscalib_mode()  local
217 	return st->syscalib_mode[chan->channel];  in ad7192_get_syscalib_mode()
225 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_write_syscalib()  local
233 	temp = st->syscalib_mode[chan->channel];  in ad7192_write_syscalib()
236 			ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,  in ad7192_write_syscalib()
239 			ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,  in ad7192_write_syscalib()
273 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);  in ad7192_set_channel()  local
275 	st->conf &= ~AD7192_CONF_CHAN_MASK;  in ad7192_set_channel()
276 	st->conf |= AD7192_CONF_CHAN(channel);  in ad7192_set_channel()
278 	return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_set_channel()
284 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);  in ad7192_set_mode()  local
286 	st->mode &= ~AD7192_MODE_SEL_MASK;  in ad7192_set_mode()
287 	st->mode |= AD7192_MODE_SEL(mode);  in ad7192_set_mode()
289 	return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_set_mode()
294 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);  in ad7192_append_status()  local
295 	unsigned int mode = st->mode;  in ad7192_append_status()
301 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);  in ad7192_append_status()
305 	st->mode = mode;  in ad7192_append_status()
312 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);  in ad7192_disable_all()  local
313 	u32 conf = st->conf;  in ad7192_disable_all()
318 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);  in ad7192_disable_all()
322 	st->conf = conf;  in ad7192_disable_all()
351 static int ad7192_calibrate_all(struct ad7192_state *st)  in ad7192_calibrate_all()  argument
353 	return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,  in ad7192_calibrate_all()
363 static int ad7192_of_clock_select(struct ad7192_state *st)  in ad7192_of_clock_select()  argument
365 	struct device_node *np = st->sd.spi->dev.of_node;  in ad7192_of_clock_select()
371 	if (st->mclk) {  in ad7192_of_clock_select()
384 static int ad7192_setup(struct ad7192_state *st, struct device_node *np)  in ad7192_setup()  argument
386 	struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);  in ad7192_setup()
393 	ret = ad_sd_reset(&st->sd, 48);  in ad7192_setup()
399 	ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);  in ad7192_setup()
405 	if (id != st->chip_info->chip_id)  in ad7192_setup()
406 		dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",  in ad7192_setup()
409 	st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |  in ad7192_setup()
410 		AD7192_MODE_CLKSRC(st->clock_sel) |  in ad7192_setup()
413 	st->conf = AD7192_CONF_GAIN(0);  in ad7192_setup()
417 		st->mode |= AD7192_MODE_REJ60;  in ad7192_setup()
420 	if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)  in ad7192_setup()
421 		st->conf |= AD7192_CONF_REFSEL;  in ad7192_setup()
423 	st->conf &= ~AD7192_CONF_CHOP;  in ad7192_setup()
424 	st->f_order = AD7192_NO_SYNC_FILTER;  in ad7192_setup()
428 		st->conf |= AD7192_CONF_BUF;  in ad7192_setup()
432 		st->conf |= AD7192_CONF_UNIPOLAR;  in ad7192_setup()
437 		st->conf |= AD7192_CONF_BURN;  in ad7192_setup()
439 		dev_warn(&st->sd.spi->dev,  in ad7192_setup()
443 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_setup()
447 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_setup()
451 	ret = ad7192_calibrate_all(st);  in ad7192_setup()
456 	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {  in ad7192_setup()
457 		scale_uv = ((u64)st->int_vref_mv * 100000000)  in ad7192_setup()
459 			((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));  in ad7192_setup()
462 		st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;  in ad7192_setup()
463 		st->scale_avail[i][0] = scale_uv;  in ad7192_setup()
474 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_show_ac_excitation()  local
476 	return sysfs_emit(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));  in ad7192_show_ac_excitation()
484 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_show_bridge_switch()  local
486 	return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));  in ad7192_show_bridge_switch()
495 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_set()  local
511 			st->gpocon |= AD7192_GPOCON_BPDSW;  in ad7192_set()
513 			st->gpocon &= ~AD7192_GPOCON_BPDSW;  in ad7192_set()
515 		ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);  in ad7192_set()
519 			st->mode |= AD7192_MODE_ACX;  in ad7192_set()
521 			st->mode &= ~AD7192_MODE_ACX;  in ad7192_set()
523 		ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_set()
534 static void ad7192_get_available_filter_freq(struct ad7192_state *st,  in ad7192_get_available_filter_freq()  argument
540 	fadc = DIV_ROUND_CLOSEST(st->fclk,  in ad7192_get_available_filter_freq()
541 				 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));  in ad7192_get_available_filter_freq()
544 	fadc = DIV_ROUND_CLOSEST(st->fclk,  in ad7192_get_available_filter_freq()
545 				 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));  in ad7192_get_available_filter_freq()
546 	freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);  in ad7192_get_available_filter_freq()
548 	fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));  in ad7192_get_available_filter_freq()
558 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_show_filter_avail()  local
562 	ad7192_get_available_filter_freq(st, freq_avail);  in ad7192_show_filter_avail()
569 	buf[len - 1] = '\n';  in ad7192_show_filter_avail()
611 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,  in ad7192_set_3db_filter_freq()  argument
621 	ad7192_get_available_filter_freq(st, freq_avail);  in ad7192_set_3db_filter_freq()
633 		st->f_order = AD7192_SYNC4_FILTER;  in ad7192_set_3db_filter_freq()
634 		st->mode &= ~AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
636 		st->conf |= AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
638 	case 1:  in ad7192_set_3db_filter_freq()
639 		st->f_order = AD7192_SYNC3_FILTER;  in ad7192_set_3db_filter_freq()
640 		st->mode |= AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
642 		st->conf |= AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
645 		st->f_order = AD7192_NO_SYNC_FILTER;  in ad7192_set_3db_filter_freq()
646 		st->mode &= ~AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
648 		st->conf &= ~AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
651 		st->f_order = AD7192_NO_SYNC_FILTER;  in ad7192_set_3db_filter_freq()
652 		st->mode |= AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
654 		st->conf &= ~AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
658 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_set_3db_filter_freq()
662 	return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_set_3db_filter_freq()
665 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)  in ad7192_get_3db_filter_freq()  argument
669 	fadc = DIV_ROUND_CLOSEST(st->fclk,  in ad7192_get_3db_filter_freq()
670 				 st->f_order * AD7192_MODE_RATE(st->mode));  in ad7192_get_3db_filter_freq()
672 	if (st->conf & AD7192_CONF_CHOP)  in ad7192_get_3db_filter_freq()
674 	if (st->mode & AD7192_MODE_SINC3)  in ad7192_get_3db_filter_freq()
686 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_read_raw()  local
687 	bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);  in ad7192_read_raw()
695 			mutex_lock(&st->lock);  in ad7192_read_raw()
696 			*val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];  in ad7192_read_raw()
697 			*val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];  in ad7192_read_raw()
698 			mutex_unlock(&st->lock);  in ad7192_read_raw()
709 			*val = -(1 << (chan->scan_type.realbits - 1));  in ad7192_read_raw()
717 		*val = st->fclk /  in ad7192_read_raw()
718 			(st->f_order * 1024 * AD7192_MODE_RATE(st->mode));  in ad7192_read_raw()
721 		*val = ad7192_get_3db_filter_freq(st);  in ad7192_read_raw()
735 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_write_raw()  local
746 		mutex_lock(&st->lock);  in ad7192_write_raw()
747 		for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)  in ad7192_write_raw()
748 			if (val2 == st->scale_avail[i][1]) {  in ad7192_write_raw()
750 				tmp = st->conf;  in ad7192_write_raw()
751 				st->conf &= ~AD7192_CONF_GAIN(-1);  in ad7192_write_raw()
752 				st->conf |= AD7192_CONF_GAIN(i);  in ad7192_write_raw()
753 				if (tmp == st->conf)  in ad7192_write_raw()
755 				ad_sd_write_reg(&st->sd, AD7192_REG_CONF,  in ad7192_write_raw()
756 						3, st->conf);  in ad7192_write_raw()
757 				ad7192_calibrate_all(st);  in ad7192_write_raw()
760 		mutex_unlock(&st->lock);  in ad7192_write_raw()
768 		div = st->fclk / (val * st->f_order * 1024);  in ad7192_write_raw()
769 		if (div < 1 || div > 1023) {  in ad7192_write_raw()
774 		st->mode &= ~AD7192_MODE_RATE(-1);  in ad7192_write_raw()
775 		st->mode |= AD7192_MODE_RATE(div);  in ad7192_write_raw()
776 		ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_write_raw()
779 		ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);  in ad7192_write_raw()
811 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_read_avail()  local
815 		*vals = (int *)st->scale_avail;  in ad7192_read_avail()
818 		*length = ARRAY_SIZE(st->scale_avail) * 2;  in ad7192_read_avail()
828 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_update_scan_mode()  local
829 	u32 conf = st->conf;  in ad7192_update_scan_mode()
837 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);  in ad7192_update_scan_mode()
841 	st->conf = conf;  in ad7192_update_scan_mode()
870 		.differential = ((_channel2) == -1 ? 0 : 1), \
871 		.indexed = 1, \
898 	__AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
902 	__AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \
906 	__AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
909 	AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
910 	AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
913 	AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
921 	AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
922 	AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
927 	AD719x_CHANNEL(6, 1, AD7193_CH_AIN1),
959 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_channels_config()  local
961 	switch (st->chip_info->chip_id) {  in ad7192_channels_config()
987 	struct ad7192_state *st;  in ad7192_probe()  local
996 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));  in ad7192_probe()
1000 	st = iio_priv(indio_dev);  in ad7192_probe()
1002 	mutex_init(&st->lock);  in ad7192_probe()
1004 	st->avdd = devm_regulator_get(&spi->dev, "avdd");  in ad7192_probe()
1005 	if (IS_ERR(st->avdd))  in ad7192_probe()
1006 		return PTR_ERR(st->avdd);  in ad7192_probe()
1008 	ret = regulator_enable(st->avdd);  in ad7192_probe()
1014 	ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd);  in ad7192_probe()
1018 	st->dvdd = devm_regulator_get(&spi->dev, "dvdd");  in ad7192_probe()
1019 	if (IS_ERR(st->dvdd))  in ad7192_probe()
1020 		return PTR_ERR(st->dvdd);  in ad7192_probe()
1022 	ret = regulator_enable(st->dvdd);  in ad7192_probe()
1028 	ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->dvdd);  in ad7192_probe()
1032 	ret = regulator_get_voltage(st->avdd);  in ad7192_probe()
1037 	st->int_vref_mv = ret / 1000;  in ad7192_probe()
1039 	st->chip_info = of_device_get_match_data(&spi->dev);  in ad7192_probe()
1040 	indio_dev->name = st->chip_info->name;  in ad7192_probe()
1047 	if (st->chip_info->chip_id == CHIPID_AD7195)  in ad7192_probe()
1052 	ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);  in ad7192_probe()
1058 	st->fclk = AD7192_INT_FREQ_MHZ;  in ad7192_probe()
1060 	st->mclk = devm_clk_get_optional(&spi->dev, "mclk");  in ad7192_probe()
1061 	if (IS_ERR(st->mclk))  in ad7192_probe()
1062 		return PTR_ERR(st->mclk);  in ad7192_probe()
1064 	st->clock_sel = ad7192_of_clock_select(st);  in ad7192_probe()
1066 	if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||  in ad7192_probe()
1067 	    st->clock_sel == AD7192_CLK_EXT_MCLK2) {  in ad7192_probe()
1068 		ret = clk_prepare_enable(st->mclk);  in ad7192_probe()
1073 					       st->mclk);  in ad7192_probe()
1077 		st->fclk = clk_get_rate(st->mclk);  in ad7192_probe()
1078 		if (!ad7192_valid_external_frequency(st->fclk)) {  in ad7192_probe()
1085 	ret = ad7192_setup(st, spi->dev.of_node);  in ad7192_probe()