273 static int adxl367_set_measure_en(struct adxl367_state *st, bool en)  in adxl367_set_measure_en()  argument
279 	ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL,  in adxl367_set_measure_en()
296 static void adxl367_scale_act_thresholds(struct adxl367_state *st,  in adxl367_scale_act_thresholds()  argument
300 	st->act_threshold = st->act_threshold  in adxl367_scale_act_thresholds()
303 	st->inact_threshold = st->inact_threshold  in adxl367_scale_act_thresholds()
308 static int _adxl367_set_act_threshold(struct adxl367_state *st,  in _adxl367_set_act_threshold()  argument
318 	st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK,  in _adxl367_set_act_threshold()
321 	st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK,  in _adxl367_set_act_threshold()
325 	ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf,  in _adxl367_set_act_threshold()
326 				sizeof(st->act_threshold_buf));  in _adxl367_set_act_threshold()
331 		st->act_threshold = threshold;  in _adxl367_set_act_threshold()
333 		st->inact_threshold = threshold;  in _adxl367_set_act_threshold()
338 static int adxl367_set_act_threshold(struct adxl367_state *st,  in adxl367_set_act_threshold()  argument
344 	mutex_lock(&st->lock);  in adxl367_set_act_threshold()
346 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_act_threshold()
350 	ret = _adxl367_set_act_threshold(st, act, threshold);  in adxl367_set_act_threshold()
354 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_act_threshold()
357 	mutex_unlock(&st->lock);  in adxl367_set_act_threshold()
362 static int adxl367_set_act_proc_mode(struct adxl367_state *st,  in adxl367_set_act_proc_mode()  argument
365 	return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,  in adxl367_set_act_proc_mode()
371 static int adxl367_set_act_interrupt_en(struct adxl367_state *st,  in adxl367_set_act_interrupt_en()  argument
377 	return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,  in adxl367_set_act_interrupt_en()
381 static int adxl367_get_act_interrupt_en(struct adxl367_state *st,  in adxl367_get_act_interrupt_en()  argument
389 	ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);  in adxl367_get_act_interrupt_en()
398 static int adxl367_set_act_en(struct adxl367_state *st,  in adxl367_set_act_en()  argument
404 	return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,  in adxl367_set_act_en()
409 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,  in adxl367_set_fifo_watermark_interrupt_en()  argument
412 	return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,  in adxl367_set_fifo_watermark_interrupt_en()
417 static int adxl367_get_fifo_mode(struct adxl367_state *st,  in adxl367_get_fifo_mode()  argument
423 	ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val);  in adxl367_get_fifo_mode()
432 static int adxl367_set_fifo_mode(struct adxl367_state *st,  in adxl367_set_fifo_mode()  argument
435 	return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,  in adxl367_set_fifo_mode()
441 static int adxl367_set_fifo_format(struct adxl367_state *st,  in adxl367_set_fifo_format()  argument
444 	return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,  in adxl367_set_fifo_format()
450 static int adxl367_set_fifo_watermark(struct adxl367_state *st,  in adxl367_set_fifo_watermark()  argument
453 	unsigned int fifo_samples = fifo_watermark * st->fifo_set_size;  in adxl367_set_fifo_watermark()
460 	fifo_samples /= st->fifo_set_size;  in adxl367_set_fifo_watermark()
469 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,  in adxl367_set_fifo_watermark()
474 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES,  in adxl367_set_fifo_watermark()
479 	st->fifo_watermark = fifo_watermark;  in adxl367_set_fifo_watermark()
487 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_set_range()  local
494 	mutex_lock(&st->lock);  in adxl367_set_range()
496 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_range()
500 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,  in adxl367_set_range()
507 	adxl367_scale_act_thresholds(st, st->range, range);  in adxl367_set_range()
510 	ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,  in adxl367_set_range()
511 					 st->act_threshold);  in adxl367_set_range()
515 	ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,  in adxl367_set_range()
516 					 st->inact_threshold);  in adxl367_set_range()
520 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_range()
524 	st->range = range;  in adxl367_set_range()
527 	mutex_unlock(&st->lock);  in adxl367_set_range()
534 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms)  in adxl367_time_ms_to_samples()  argument
536 	int freq_hz = adxl367_samp_freq_tbl[st->odr][0];  in adxl367_time_ms_to_samples()
537 	int freq_microhz = adxl367_samp_freq_tbl[st->odr][1];  in adxl367_time_ms_to_samples()
544 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms)  in _adxl367_set_act_time_ms()  argument
546 	unsigned int val = adxl367_time_ms_to_samples(st, ms);  in _adxl367_set_act_time_ms()
552 	ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val);  in _adxl367_set_act_time_ms()
556 	st->act_time_ms = ms;  in _adxl367_set_act_time_ms()
561 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms)  in _adxl367_set_inact_time_ms()  argument
563 	unsigned int val = adxl367_time_ms_to_samples(st, ms);  in _adxl367_set_inact_time_ms()
569 	st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK,  in _adxl367_set_inact_time_ms()
572 	st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK,  in _adxl367_set_inact_time_ms()
576 	ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H,  in _adxl367_set_inact_time_ms()
577 				st->inact_time_buf, sizeof(st->inact_time_buf));  in _adxl367_set_inact_time_ms()
581 	st->inact_time_ms = ms;  in _adxl367_set_inact_time_ms()
586 static int adxl367_set_act_time_ms(struct adxl367_state *st,  in adxl367_set_act_time_ms()  argument
592 	mutex_lock(&st->lock);  in adxl367_set_act_time_ms()
594 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_act_time_ms()
599 		ret = _adxl367_set_act_time_ms(st, ms);  in adxl367_set_act_time_ms()
601 		ret = _adxl367_set_inact_time_ms(st, ms);  in adxl367_set_act_time_ms()
606 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_act_time_ms()
609 	mutex_unlock(&st->lock);  in adxl367_set_act_time_ms()
614 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr)  in _adxl367_set_odr()  argument
618 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,  in _adxl367_set_odr()
626 	ret = _adxl367_set_act_time_ms(st, st->act_time_ms);  in _adxl367_set_odr()
630 	ret = _adxl367_set_inact_time_ms(st, st->inact_time_ms);  in _adxl367_set_odr()
634 	st->odr = odr;  in _adxl367_set_odr()
641 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_set_odr()  local
648 	mutex_lock(&st->lock);  in adxl367_set_odr()
650 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_odr()
654 	ret = _adxl367_set_odr(st, odr);  in adxl367_set_odr()
658 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_odr()
661 	mutex_unlock(&st->lock);  in adxl367_set_odr()
668 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg,  in adxl367_set_temp_adc_en()  argument
671 	return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK,  in adxl367_set_temp_adc_en()
675 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st,  in adxl367_set_temp_adc_reg_en()  argument
682 		ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);  in adxl367_set_temp_adc_reg_en()
685 		ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);  in adxl367_set_temp_adc_reg_en()
700 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st,  in adxl367_set_temp_adc_mask_en()  argument
705 		return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);  in adxl367_set_temp_adc_mask_en()
707 		return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);  in adxl367_set_temp_adc_mask_en()
712 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2,  in adxl367_find_odr()  argument
731 static int adxl367_find_range(struct adxl367_state *st, int val, int val2,  in adxl367_find_range()  argument
754 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_sample()  local
762 	mutex_lock(&st->lock);  in adxl367_read_sample()
764 	ret = adxl367_set_temp_adc_reg_en(st, chan->address, true);  in adxl367_read_sample()
768 	ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf,  in adxl367_read_sample()
769 			       sizeof(st->sample_buf));  in adxl367_read_sample()
773 	sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf));  in adxl367_read_sample()
776 	ret = adxl367_set_temp_adc_reg_en(st, chan->address, false);  in adxl367_read_sample()
779 	mutex_unlock(&st->lock);  in adxl367_read_sample()
786 static int adxl367_get_status(struct adxl367_state *st, u8 *status,  in adxl367_get_status()  argument
792 	ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS,  in adxl367_get_status()
793 			       st->status_buf, sizeof(st->status_buf));  in adxl367_get_status()
797 	st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK;  in adxl367_get_status()
799 	*status = st->status_buf[0];  in adxl367_get_status()
800 	*fifo_entries = get_unaligned_le16(&st->status_buf[1]);  in adxl367_get_status()
827 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_push_fifo_data()  local
834 	fifo_entries -= fifo_entries % st->fifo_set_size;  in adxl367_push_fifo_data()
836 	ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries);  in adxl367_push_fifo_data()
838 		dev_err(st->dev, "Failed to read FIFO: %d\n", ret);  in adxl367_push_fifo_data()
842 	for (i = 0; i < fifo_entries; i += st->fifo_set_size)  in adxl367_push_fifo_data()
843 		iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);  in adxl367_push_fifo_data()
851 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_irq_handler()  local
857 	ret = adxl367_get_status(st, &status, &fifo_entries);  in adxl367_irq_handler()
872 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_reg_access()  local
875 		return regmap_read(st->regmap, reg, readval);  in adxl367_reg_access()
877 		return regmap_write(st->regmap, reg, writeval);  in adxl367_reg_access()
884 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_raw()  local
892 			mutex_lock(&st->lock);  in adxl367_read_raw()
893 			*val = adxl367_range_scale_tbl[st->range][0];  in adxl367_read_raw()
894 			*val2 = adxl367_range_scale_tbl[st->range][1];  in adxl367_read_raw()
895 			mutex_unlock(&st->lock);  in adxl367_read_raw()
920 		mutex_lock(&st->lock);  in adxl367_read_raw()
921 		*val = adxl367_samp_freq_tbl[st->odr][0];  in adxl367_read_raw()
922 		*val2 = adxl367_samp_freq_tbl[st->odr][1];  in adxl367_read_raw()
923 		mutex_unlock(&st->lock);  in adxl367_read_raw()
934 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_write_raw()  local
941 		ret = adxl367_find_odr(st, val, val2, &odr);  in adxl367_write_raw()
950 		ret = adxl367_find_range(st, val, val2, &range);  in adxl367_write_raw()
1007 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_event_value()  local
1013 			mutex_lock(&st->lock);  in adxl367_read_event_value()
1014 			*val = st->act_threshold;  in adxl367_read_event_value()
1015 			mutex_unlock(&st->lock);  in adxl367_read_event_value()
1018 			mutex_lock(&st->lock);  in adxl367_read_event_value()
1019 			*val = st->inact_threshold;  in adxl367_read_event_value()
1020 			mutex_unlock(&st->lock);  in adxl367_read_event_value()
1029 			mutex_lock(&st->lock);  in adxl367_read_event_value()
1030 			*val = st->act_time_ms;  in adxl367_read_event_value()
1031 			mutex_unlock(&st->lock);  in adxl367_read_event_value()
1035 			mutex_lock(&st->lock);  in adxl367_read_event_value()
1036 			*val = st->inact_time_ms;  in adxl367_read_event_value()
1037 			mutex_unlock(&st->lock);  in adxl367_read_event_value()
1055 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_write_event_value()  local
1064 			return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val);  in adxl367_write_event_value()
1066 			return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val);  in adxl367_write_event_value()
1077 			return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val);  in adxl367_write_event_value()
1079 			return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val);  in adxl367_write_event_value()
1093 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_event_config()  local
1099 		ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en);  in adxl367_read_event_config()
1102 		ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en);  in adxl367_read_event_config()
1115 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_write_event_config()  local
1134 	mutex_lock(&st->lock);  in adxl367_write_event_config()
1136 	ret = adxl367_set_measure_en(st, false);  in adxl367_write_event_config()
1140 	ret = adxl367_set_act_interrupt_en(st, act, state);  in adxl367_write_event_config()
1144 	ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED  in adxl367_write_event_config()
1149 	ret = adxl367_set_measure_en(st, true);  in adxl367_write_event_config()
1152 	mutex_unlock(&st->lock);  in adxl367_write_event_config()
1163 	struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));  in adxl367_get_fifo_enabled()  local
1167 	ret = adxl367_get_fifo_mode(st, &fifo_mode);  in adxl367_get_fifo_enabled()
1178 	struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));  in adxl367_get_fifo_watermark()  local
1181 	mutex_lock(&st->lock);  in adxl367_get_fifo_watermark()
1182 	fifo_watermark = st->fifo_watermark;  in adxl367_get_fifo_watermark()
1183 	mutex_unlock(&st->lock);  in adxl367_get_fifo_watermark()
1219 	struct adxl367_state *st  = iio_priv(indio_dev);  in adxl367_set_watermark()  local
1225 	mutex_lock(&st->lock);  in adxl367_set_watermark()
1227 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_watermark()
1231 	ret = adxl367_set_fifo_watermark(st, val);  in adxl367_set_watermark()
1235 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_watermark()
1238 	mutex_unlock(&st->lock);  in adxl367_set_watermark()
1264 	struct adxl367_state *st  = iio_priv(indio_dev);  in adxl367_update_scan_mode()  local
1271 	mutex_lock(&st->lock);  in adxl367_update_scan_mode()
1273 	ret = adxl367_set_measure_en(st, false);  in adxl367_update_scan_mode()
1277 	ret = adxl367_set_fifo_format(st, fifo_format);  in adxl367_update_scan_mode()
1281 	ret = adxl367_set_measure_en(st, true);  in adxl367_update_scan_mode()
1285 	st->fifo_set_size = bitmap_weight(active_scan_mask,  in adxl367_update_scan_mode()
1289 	mutex_unlock(&st->lock);  in adxl367_update_scan_mode()
1296 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_buffer_postenable()  local
1299 	mutex_lock(&st->lock);  in adxl367_buffer_postenable()
1301 	ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,  in adxl367_buffer_postenable()
1306 	ret = adxl367_set_measure_en(st, false);  in adxl367_buffer_postenable()
1310 	ret = adxl367_set_fifo_watermark_interrupt_en(st, true);  in adxl367_buffer_postenable()
1314 	ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM);  in adxl367_buffer_postenable()
1318 	ret = adxl367_set_measure_en(st, true);  in adxl367_buffer_postenable()
1321 	mutex_unlock(&st->lock);  in adxl367_buffer_postenable()
1328 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_buffer_predisable()  local
1331 	mutex_lock(&st->lock);  in adxl367_buffer_predisable()
1333 	ret = adxl367_set_measure_en(st, false);  in adxl367_buffer_predisable()
1337 	ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED);  in adxl367_buffer_predisable()
1341 	ret = adxl367_set_fifo_watermark_interrupt_en(st, false);  in adxl367_buffer_predisable()
1345 	ret = adxl367_set_measure_en(st, true);  in adxl367_buffer_predisable()
1349 	ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,  in adxl367_buffer_predisable()
1353 	mutex_unlock(&st->lock);  in adxl367_buffer_predisable()
1442 static int adxl367_verify_devid(struct adxl367_state *st)  in adxl367_verify_devid()  argument
1447 	ret = regmap_read_poll_timeout(st->regmap, ADXL367_REG_DEVID, val,  in adxl367_verify_devid()
1450 		return dev_err_probe(st->dev, -ENODEV,  in adxl367_verify_devid()
1457 static int adxl367_setup(struct adxl367_state *st)  in adxl367_setup()  argument
1461 	ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,  in adxl367_setup()
1466 	ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,  in adxl367_setup()
1471 	ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED);  in adxl367_setup()
1475 	ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ);  in adxl367_setup()
1479 	ret = _adxl367_set_act_time_ms(st, 10);  in adxl367_setup()
1483 	ret = _adxl367_set_inact_time_ms(st, 10000);  in adxl367_setup()
1487 	return adxl367_set_measure_en(st, true);  in adxl367_setup()
1492 	struct adxl367_state *st = data;  in adxl367_disable_regulators()  local
1494 	regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);  in adxl367_disable_regulators()
1501 	struct adxl367_state *st;  in adxl367_probe()  local
1504 	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));  in adxl367_probe()
1508 	st = iio_priv(indio_dev);  in adxl367_probe()
1509 	st->dev = dev;  in adxl367_probe()
1510 	st->regmap = regmap;  in adxl367_probe()
1511 	st->context = context;  in adxl367_probe()
1512 	st->ops = ops;  in adxl367_probe()
1514 	mutex_init(&st->lock);  in adxl367_probe()
1523 	st->regulators[0].supply = "vdd";  in adxl367_probe()
1524 	st->regulators[1].supply = "vddio";  in adxl367_probe()
1526 	ret = devm_regulator_bulk_get(st->dev, ARRAY_SIZE(st->regulators),  in adxl367_probe()
1527 				      st->regulators);  in adxl367_probe()
1529 		return dev_err_probe(st->dev, ret,  in adxl367_probe()
1532 	ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);  in adxl367_probe()
1534 		return dev_err_probe(st->dev, ret,  in adxl367_probe()
1537 	ret = devm_add_action_or_reset(st->dev, adxl367_disable_regulators, st);  in adxl367_probe()
1539 		return dev_err_probe(st->dev, ret,  in adxl367_probe()
1542 	ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE);  in adxl367_probe()
1546 	ret = adxl367_verify_devid(st);  in adxl367_probe()
1550 	ret = adxl367_setup(st);  in adxl367_probe()
1554 	ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,  in adxl367_probe()
1560 	ret = devm_request_threaded_irq(st->dev, irq, NULL,  in adxl367_probe()
1564 		return dev_err_probe(st->dev, ret, "Failed to request irq\n");  in adxl367_probe()