Lines Matching full:i2c
3 * i2c-xiic.c
24 #include <linux/i2c.h>
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
48 * struct xiic_i2c - Internal representation of the XIIC I2C bus
172 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) argument
173 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) argument
175 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
176 static void __xiic_start_xfer(struct xiic_i2c *i2c);
186 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) in xiic_setreg8() argument
188 if (i2c->endianness == LITTLE) in xiic_setreg8()
189 iowrite8(value, i2c->base + reg); in xiic_setreg8()
191 iowrite8(value, i2c->base + reg + 3); in xiic_setreg8()
194 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) in xiic_getreg8() argument
198 if (i2c->endianness == LITTLE) in xiic_getreg8()
199 ret = ioread8(i2c->base + reg); in xiic_getreg8()
201 ret = ioread8(i2c->base + reg + 3); in xiic_getreg8()
205 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) in xiic_setreg16() argument
207 if (i2c->endianness == LITTLE) in xiic_setreg16()
208 iowrite16(value, i2c->base + reg); in xiic_setreg16()
210 iowrite16be(value, i2c->base + reg + 2); in xiic_setreg16()
213 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) in xiic_setreg32() argument
215 if (i2c->endianness == LITTLE) in xiic_setreg32()
216 iowrite32(value, i2c->base + reg); in xiic_setreg32()
218 iowrite32be(value, i2c->base + reg); in xiic_setreg32()
221 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) in xiic_getreg32() argument
225 if (i2c->endianness == LITTLE) in xiic_getreg32()
226 ret = ioread32(i2c->base + reg); in xiic_getreg32()
228 ret = ioread32be(i2c->base + reg); in xiic_getreg32()
232 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) in xiic_irq_dis() argument
234 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_irq_dis()
236 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); in xiic_irq_dis()
239 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) in xiic_irq_en() argument
241 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_irq_en()
243 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); in xiic_irq_en()
246 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) in xiic_irq_clr() argument
248 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_irq_clr()
250 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); in xiic_irq_clr()
253 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) in xiic_irq_clr_en() argument
255 xiic_irq_clr(i2c, mask); in xiic_irq_clr_en()
256 xiic_irq_en(i2c, mask); in xiic_irq_clr_en()
259 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) in xiic_clear_rx_fifo() argument
265 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); in xiic_clear_rx_fifo()
267 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { in xiic_clear_rx_fifo()
268 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_clear_rx_fifo()
270 dev_err(i2c->dev, "Failed to clear rx fifo\n"); in xiic_clear_rx_fifo()
278 static int xiic_reinit(struct xiic_i2c *i2c) in xiic_reinit() argument
282 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); in xiic_reinit()
285 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); in xiic_reinit()
288 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); in xiic_reinit()
291 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); in xiic_reinit()
294 ret = xiic_clear_rx_fifo(i2c); in xiic_reinit()
299 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); in xiic_reinit()
301 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); in xiic_reinit()
306 static void xiic_deinit(struct xiic_i2c *i2c) in xiic_deinit() argument
310 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); in xiic_deinit()
313 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_deinit()
314 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); in xiic_deinit()
317 static void xiic_read_rx(struct xiic_i2c *i2c) in xiic_read_rx() argument
322 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; in xiic_read_rx()
324 dev_dbg(i2c->adap.dev.parent, in xiic_read_rx()
326 __func__, bytes_in_fifo, xiic_rx_space(i2c), in xiic_read_rx()
327 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), in xiic_read_rx()
328 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_read_rx()
330 if (bytes_in_fifo > xiic_rx_space(i2c)) in xiic_read_rx()
331 bytes_in_fifo = xiic_rx_space(i2c); in xiic_read_rx()
334 i2c->rx_msg->buf[i2c->rx_pos++] = in xiic_read_rx()
335 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_read_rx()
337 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, in xiic_read_rx()
338 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? in xiic_read_rx()
339 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); in xiic_read_rx()
342 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) in xiic_tx_fifo_space() argument
345 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; in xiic_tx_fifo_space()
348 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) in xiic_fill_tx_fifo() argument
350 u8 fifo_space = xiic_tx_fifo_space(i2c); in xiic_fill_tx_fifo()
351 int len = xiic_tx_space(i2c); in xiic_fill_tx_fifo()
355 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", in xiic_fill_tx_fifo()
359 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; in xiic_fill_tx_fifo()
361 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { in xiic_fill_tx_fifo()
364 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); in xiic_fill_tx_fifo()
366 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_fill_tx_fifo()
370 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code) in xiic_wakeup() argument
372 i2c->tx_msg = NULL; in xiic_wakeup()
373 i2c->rx_msg = NULL; in xiic_wakeup()
374 i2c->nmsgs = 0; in xiic_wakeup()
375 i2c->state = code; in xiic_wakeup()
376 complete(&i2c->completion); in xiic_wakeup()
381 struct xiic_i2c *i2c = dev_id; in xiic_process() local
394 mutex_lock(&i2c->lock); in xiic_process()
395 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_process()
396 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_process()
399 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", in xiic_process()
401 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", in xiic_process()
402 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), in xiic_process()
403 i2c->tx_msg, i2c->nmsgs); in xiic_process()
416 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); in xiic_process()
422 ret = xiic_reinit(i2c); in xiic_process()
424 dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); in xiic_process()
426 if (i2c->rx_msg) { in xiic_process()
430 if (i2c->tx_msg) { in xiic_process()
439 if (!i2c->rx_msg) { in xiic_process()
440 dev_dbg(i2c->adap.dev.parent, in xiic_process()
442 xiic_clear_rx_fifo(i2c); in xiic_process()
446 xiic_read_rx(i2c); in xiic_process()
447 if (xiic_rx_space(i2c) == 0) { in xiic_process()
449 i2c->rx_msg = NULL; in xiic_process()
454 dev_dbg(i2c->adap.dev.parent, in xiic_process()
456 __func__, i2c->nmsgs); in xiic_process()
462 if (i2c->nmsgs > 1) { in xiic_process()
463 i2c->nmsgs--; in xiic_process()
464 i2c->tx_msg++; in xiic_process()
465 dev_dbg(i2c->adap.dev.parent, in xiic_process()
477 if (!i2c->tx_msg) { in xiic_process()
478 dev_dbg(i2c->adap.dev.parent, in xiic_process()
483 xiic_fill_tx_fifo(i2c); in xiic_process()
486 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { in xiic_process()
487 dev_dbg(i2c->adap.dev.parent, in xiic_process()
489 __func__, i2c->nmsgs); in xiic_process()
490 if (i2c->nmsgs > 1) { in xiic_process()
491 i2c->nmsgs--; in xiic_process()
492 i2c->tx_msg++; in xiic_process()
495 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); in xiic_process()
497 dev_dbg(i2c->adap.dev.parent, in xiic_process()
501 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) in xiic_process()
505 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); in xiic_process()
513 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); in xiic_process()
515 if (!i2c->tx_msg) in xiic_process()
520 if (i2c->nmsgs == 1 && !i2c->rx_msg && in xiic_process()
521 xiic_tx_space(i2c) == 0) in xiic_process()
528 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); in xiic_process()
530 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); in xiic_process()
532 __xiic_start_xfer(i2c); in xiic_process()
534 xiic_wakeup(i2c, wakeup_code); in xiic_process()
538 mutex_unlock(&i2c->lock); in xiic_process()
542 static int xiic_bus_busy(struct xiic_i2c *i2c) in xiic_bus_busy() argument
544 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); in xiic_bus_busy()
549 static int xiic_busy(struct xiic_i2c *i2c) in xiic_busy() argument
554 if (i2c->tx_msg || i2c->rx_msg) in xiic_busy()
559 * should ignore it, since bus will never be released and i2c will be in xiic_busy()
562 if (i2c->singlemaster) { in xiic_busy()
570 err = xiic_bus_busy(i2c); in xiic_busy()
573 err = xiic_bus_busy(i2c); in xiic_busy()
579 static void xiic_start_recv(struct xiic_i2c *i2c) in xiic_start_recv() argument
582 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; in xiic_start_recv()
585 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); in xiic_start_recv()
596 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, (u8)(rx_watermark - 1)); in xiic_start_recv()
600 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, in xiic_start_recv()
603 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); in xiic_start_recv()
605 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, in xiic_start_recv()
606 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); in xiic_start_recv()
608 if (i2c->nmsgs == 1) in xiic_start_recv()
610 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); in xiic_start_recv()
613 i2c->tx_pos = msg->len; in xiic_start_recv()
616 static void xiic_start_send(struct xiic_i2c *i2c) in xiic_start_send() argument
618 struct i2c_msg *msg = i2c->tx_msg; in xiic_start_send()
620 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", in xiic_start_send()
622 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", in xiic_start_send()
623 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_start_send()
624 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_start_send()
630 if ((i2c->nmsgs == 1) && msg->len == 0) in xiic_start_send()
634 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_start_send()
638 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | in xiic_start_send()
640 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? in xiic_start_send()
643 xiic_fill_tx_fifo(i2c); in xiic_start_send()
646 static void __xiic_start_xfer(struct xiic_i2c *i2c) in __xiic_start_xfer() argument
648 int fifo_space = xiic_tx_fifo_space(i2c); in __xiic_start_xfer()
650 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", in __xiic_start_xfer()
651 __func__, i2c->tx_msg, fifo_space); in __xiic_start_xfer()
653 if (!i2c->tx_msg) in __xiic_start_xfer()
656 i2c->rx_pos = 0; in __xiic_start_xfer()
657 i2c->tx_pos = 0; in __xiic_start_xfer()
658 i2c->state = STATE_START; in __xiic_start_xfer()
659 if (i2c->tx_msg->flags & I2C_M_RD) { in __xiic_start_xfer()
661 xiic_start_recv(i2c); in __xiic_start_xfer()
663 xiic_start_send(i2c); in __xiic_start_xfer()
667 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) in xiic_start_xfer() argument
671 mutex_lock(&i2c->lock); in xiic_start_xfer()
673 ret = xiic_busy(i2c); in xiic_start_xfer()
677 i2c->tx_msg = msgs; in xiic_start_xfer()
678 i2c->rx_msg = NULL; in xiic_start_xfer()
679 i2c->nmsgs = num; in xiic_start_xfer()
680 init_completion(&i2c->completion); in xiic_start_xfer()
682 ret = xiic_reinit(i2c); in xiic_start_xfer()
684 __xiic_start_xfer(i2c); in xiic_start_xfer()
687 mutex_unlock(&i2c->lock); in xiic_start_xfer()
694 struct xiic_i2c *i2c = i2c_get_adapdata(adap); in xiic_xfer() local
698 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); in xiic_xfer()
700 err = pm_runtime_resume_and_get(i2c->dev); in xiic_xfer()
704 err = xiic_start_xfer(i2c, msgs, num); in xiic_xfer()
710 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); in xiic_xfer()
711 mutex_lock(&i2c->lock); in xiic_xfer()
713 i2c->tx_msg = NULL; in xiic_xfer()
714 i2c->rx_msg = NULL; in xiic_xfer()
715 i2c->nmsgs = 0; in xiic_xfer()
718 i2c->tx_msg = NULL; in xiic_xfer()
719 i2c->rx_msg = NULL; in xiic_xfer()
720 i2c->nmsgs = 0; in xiic_xfer()
722 err = (i2c->state == STATE_DONE) ? num : -EIO; in xiic_xfer()
724 mutex_unlock(&i2c->lock); in xiic_xfer()
725 pm_runtime_mark_last_busy(i2c->dev); in xiic_xfer()
726 pm_runtime_put_autosuspend(i2c->dev); in xiic_xfer()
753 struct xiic_i2c *i2c; in xiic_i2c_probe() local
760 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in xiic_i2c_probe()
761 if (!i2c) in xiic_i2c_probe()
765 i2c->base = devm_ioremap_resource(&pdev->dev, res); in xiic_i2c_probe()
766 if (IS_ERR(i2c->base)) in xiic_i2c_probe()
767 return PTR_ERR(i2c->base); in xiic_i2c_probe()
776 platform_set_drvdata(pdev, i2c); in xiic_i2c_probe()
777 i2c->adap = xiic_adapter; in xiic_i2c_probe()
778 i2c_set_adapdata(&i2c->adap, i2c); in xiic_i2c_probe()
779 i2c->adap.dev.parent = &pdev->dev; in xiic_i2c_probe()
780 i2c->adap.dev.of_node = pdev->dev.of_node; in xiic_i2c_probe()
781 snprintf(i2c->adap.name, sizeof(i2c->adap.name), in xiic_i2c_probe()
784 mutex_init(&i2c->lock); in xiic_i2c_probe()
786 i2c->clk = devm_clk_get(&pdev->dev, NULL); in xiic_i2c_probe()
787 if (IS_ERR(i2c->clk)) in xiic_i2c_probe()
788 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), in xiic_i2c_probe()
791 ret = clk_prepare_enable(i2c->clk); in xiic_i2c_probe()
796 i2c->dev = &pdev->dev; in xiic_i2c_probe()
797 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); in xiic_i2c_probe()
798 pm_runtime_use_autosuspend(i2c->dev); in xiic_i2c_probe()
799 pm_runtime_set_active(i2c->dev); in xiic_i2c_probe()
800 pm_runtime_enable(i2c->dev); in xiic_i2c_probe()
803 pdev->name, i2c); in xiic_i2c_probe()
810 i2c->singlemaster = in xiic_i2c_probe()
818 i2c->endianness = LITTLE; in xiic_i2c_probe()
819 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); in xiic_i2c_probe()
821 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); in xiic_i2c_probe()
823 i2c->endianness = BIG; in xiic_i2c_probe()
825 ret = xiic_reinit(i2c); in xiic_i2c_probe()
831 /* add i2c adapter to i2c tree */ in xiic_i2c_probe()
832 ret = i2c_add_adapter(&i2c->adap); in xiic_i2c_probe()
834 xiic_deinit(i2c); in xiic_i2c_probe()
841 i2c_new_client_device(&i2c->adap, pdata->devices + i); in xiic_i2c_probe()
849 clk_disable_unprepare(i2c->clk); in xiic_i2c_probe()
855 struct xiic_i2c *i2c = platform_get_drvdata(pdev); in xiic_i2c_remove() local
859 i2c_del_adapter(&i2c->adap); in xiic_i2c_remove()
861 ret = pm_runtime_resume_and_get(i2c->dev); in xiic_i2c_remove()
865 xiic_deinit(i2c); in xiic_i2c_remove()
866 pm_runtime_put_sync(i2c->dev); in xiic_i2c_remove()
867 clk_disable_unprepare(i2c->clk); in xiic_i2c_remove()
885 struct xiic_i2c *i2c = dev_get_drvdata(dev); in xiic_i2c_runtime_suspend() local
887 clk_disable(i2c->clk); in xiic_i2c_runtime_suspend()
894 struct xiic_i2c *i2c = dev_get_drvdata(dev); in xiic_i2c_runtime_resume() local
897 ret = clk_enable(i2c->clk); in xiic_i2c_runtime_resume()
925 MODULE_DESCRIPTION("Xilinx I2C bus driver");