Lines Matching +full:i2c +full:- +full:fast +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-tegra.c
14 #include <linux/dma-mapping.h>
16 #include <linux/i2c.h>
51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
154 * @MSG_END_REPEAT_START: Send repeat-start.
155 * @MSG_END_CONTINUE: Don't send stop or repeat-start.
165 * @has_continue_xfer_support: continue-transfer supported
170 * @clk_divisor_hs_mode: Clock divisor in HS mode.
171 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
172 * applicable if there is no fast clock source i.e. single clock
174 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
175 * applicable if there is no fast clock source i.e. single clock
177 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
178 * applicable if there is no fast clock source (i.e. single
180 * @has_multi_master_mode: The I2C controller supports running in single-master
181 * or multi-master mode.
182 * @has_slcg_override_reg: The I2C controller supports a register that
184 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
187 * @quirks: I2C adapter quirks for limiting write/read transfer size and not
192 * @tlow_std_mode: Low period of the clock in standard mode.
193 * @thigh_std_mode: High period of the clock in standard mode.
194 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
195 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
197 * in standard mode.
199 * conditions in fast/fast-plus modes.
201 * in HS mode.
230 * struct tegra_i2c_dev - per device I2C context
232 * @hw: Tegra I2C HW feature
233 * @adapter: core I2C layer adapter information
234 * @div_clk: clock reference for div clock of I2C controller
235 * @clocks: array of I2C controller clocks
237 * @rst: reset control for the I2C controller
239 * @base_phys: physical base address of the I2C controller
240 * @cont_id: I2C controller ID, used for packet header
242 * @is_dvc: identifies the DVC I2C controller, has a different register layout
243 * @is_vi: identifies the VI I2C controller, has a different register layout
249 * @timings: i2c timings information like bus frequency
250 * @multimaster_mode: indicates that I2C controller is in multi-master mode
302 writel_relaxed(val, i2c_dev->base + reg); in dvc_writel()
307 return readl_relaxed(i2c_dev->base + reg); in dvc_readl()
312 * in order to talk to the I2C block inside the DVC block.
316 if (i2c_dev->is_dvc) in tegra_i2c_reg_addr()
318 else if (i2c_dev->is_vi) in tegra_i2c_reg_addr()
326 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
330 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
331 else if (i2c_dev->is_vi) in i2c_writel()
332 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); in i2c_writel()
337 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_readl()
343 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_writesl()
352 * VI I2C controller has known hardware bug where writes get stuck in i2c_writesl_vi()
354 * Recommended software work around is to read I2C register after in i2c_writesl_vi()
357 while (len--) in i2c_writesl_vi()
364 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_readsl()
387 complete(&i2c_dev->dma_complete); in tegra_i2c_dma_complete()
396 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); in tegra_i2c_dma_submit()
398 reinit_completion(&i2c_dev->dma_complete); in tegra_i2c_dma_submit()
400 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; in tegra_i2c_dma_submit()
401 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; in tegra_i2c_dma_submit()
403 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, in tegra_i2c_dma_submit()
407 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", in tegra_i2c_dma_submit()
408 i2c_dev->msg_read ? "RX" : "TX"); in tegra_i2c_dma_submit()
409 return -EINVAL; in tegra_i2c_dma_submit()
412 dma_desc->callback = tegra_i2c_dma_complete; in tegra_i2c_dma_submit()
413 dma_desc->callback_param = i2c_dev; in tegra_i2c_dma_submit()
423 if (i2c_dev->dma_buf) { in tegra_i2c_release_dma()
424 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, in tegra_i2c_release_dma()
425 i2c_dev->dma_buf, i2c_dev->dma_phys); in tegra_i2c_release_dma()
426 i2c_dev->dma_buf = NULL; in tegra_i2c_release_dma()
429 if (i2c_dev->tx_dma_chan) { in tegra_i2c_release_dma()
430 dma_release_channel(i2c_dev->tx_dma_chan); in tegra_i2c_release_dma()
431 i2c_dev->tx_dma_chan = NULL; in tegra_i2c_release_dma()
434 if (i2c_dev->rx_dma_chan) { in tegra_i2c_release_dma()
435 dma_release_channel(i2c_dev->rx_dma_chan); in tegra_i2c_release_dma()
436 i2c_dev->rx_dma_chan = NULL; in tegra_i2c_release_dma()
447 if (i2c_dev->is_vi) in tegra_i2c_init_dma()
450 if (!i2c_dev->hw->has_apb_dma) { in tegra_i2c_init_dma()
452 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); in tegra_i2c_init_dma()
456 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n"); in tegra_i2c_init_dma()
460 chan = dma_request_chan(i2c_dev->dev, "rx"); in tegra_i2c_init_dma()
466 i2c_dev->rx_dma_chan = chan; in tegra_i2c_init_dma()
468 chan = dma_request_chan(i2c_dev->dev, "tx"); in tegra_i2c_init_dma()
474 i2c_dev->tx_dma_chan = chan; in tegra_i2c_init_dma()
476 WARN_ON(i2c_dev->tx_dma_chan->device != i2c_dev->rx_dma_chan->device); in tegra_i2c_init_dma()
477 i2c_dev->dma_dev = chan->device->dev; in tegra_i2c_init_dma()
479 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + in tegra_i2c_init_dma()
482 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, in tegra_i2c_init_dma()
485 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); in tegra_i2c_init_dma()
486 err = -ENOMEM; in tegra_i2c_init_dma()
490 i2c_dev->dma_buf = dma_buf; in tegra_i2c_init_dma()
491 i2c_dev->dma_phys = dma_phys; in tegra_i2c_init_dma()
497 if (err != -EPROBE_DEFER) { in tegra_i2c_init_dma()
498 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); in tegra_i2c_init_dma()
499 dev_err(i2c_dev->dev, "falling back to PIO\n"); in tegra_i2c_init_dma()
507 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
508 * block. This block is identical to the rest of the I2C blocks, except that
509 * it only supports master mode, it has registers moved around, and it needs
510 * some extra init to get it into I2C mode. The register moves are handled
560 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); in tegra_i2c_poll_register()
563 if (!i2c_dev->atomic_mode) in tegra_i2c_poll_register()
576 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_flush_fifos()
592 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); in tegra_i2c_flush_fifos()
603 if (!i2c_dev->hw->has_config_load_reg) in tegra_i2c_wait_for_config_load()
611 dev_err(i2c_dev->dev, "failed to load config\n"); in tegra_i2c_wait_for_config_load()
621 acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); in tegra_i2c_init()
622 struct i2c_timings *t = &i2c_dev->timings; in tegra_i2c_init()
629 * kernel boot up since voltage regulators use I2C. Hence, we will in tegra_i2c_init()
636 err = reset_control_reset(i2c_dev->rst); in tegra_i2c_init()
640 if (i2c_dev->is_dvc) in tegra_i2c_init()
646 if (i2c_dev->hw->has_multi_master_mode) in tegra_i2c_init()
652 if (i2c_dev->is_vi) in tegra_i2c_init()
655 switch (t->bus_freq_hz) { in tegra_i2c_init()
658 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; in tegra_i2c_init()
659 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; in tegra_i2c_init()
660 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; in tegra_i2c_init()
662 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) in tegra_i2c_init()
663 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; in tegra_i2c_init()
665 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; in tegra_i2c_init()
669 tlow = i2c_dev->hw->tlow_std_mode; in tegra_i2c_init()
670 thigh = i2c_dev->hw->thigh_std_mode; in tegra_i2c_init()
671 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; in tegra_i2c_init()
672 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; in tegra_i2c_init()
678 i2c_dev->hw->clk_divisor_hs_mode) | in tegra_i2c_init()
682 if (i2c_dev->hw->has_interface_timing_reg) { in tegra_i2c_init()
689 * Configure setup and hold times only when tsu_thd is non-zero. in tegra_i2c_init()
692 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) in tegra_i2c_init()
697 err = clk_set_rate(i2c_dev->div_clk, in tegra_i2c_init()
698 t->bus_freq_hz * clk_multiplier); in tegra_i2c_init()
700 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); in tegra_i2c_init()
704 if (!i2c_dev->is_dvc && !i2c_dev->is_vi) { in tegra_i2c_init()
717 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) in tegra_i2c_init()
732 * NACK interrupt is generated before the I2C controller generates in tegra_i2c_disable_packet_mode()
737 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); in tegra_i2c_disable_packet_mode()
748 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_empty_rx_fifo()
750 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_empty_rx_fifo()
757 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) in tegra_i2c_empty_rx_fifo()
758 return -EINVAL; in tegra_i2c_empty_rx_fifo()
760 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_empty_rx_fifo()
776 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_empty_rx_fifo()
777 rx_fifo_avail -= words_to_transfer; in tegra_i2c_empty_rx_fifo()
793 rx_fifo_avail--; in tegra_i2c_empty_rx_fifo()
798 return -EINVAL; in tegra_i2c_empty_rx_fifo()
800 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_empty_rx_fifo()
801 i2c_dev->msg_buf = buf; in tegra_i2c_empty_rx_fifo()
808 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_fill_tx_fifo()
810 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_fill_tx_fifo()
813 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_fill_tx_fifo()
841 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_fill_tx_fifo()
842 tx_fifo_avail -= words_to_transfer; in tegra_i2c_fill_tx_fifo()
844 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_fill_tx_fifo()
845 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_fill_tx_fifo()
847 if (i2c_dev->is_vi) in tegra_i2c_fill_tx_fifo()
864 * in this function for non-zero words_to_transfer. in tegra_i2c_fill_tx_fifo()
869 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_fill_tx_fifo()
870 i2c_dev->msg_buf = NULL; in tegra_i2c_fill_tx_fifo()
887 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", in tegra_i2c_isr()
891 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
898 i2c_dev->msg_err |= I2C_ERR_NO_ACK; in tegra_i2c_isr()
900 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; in tegra_i2c_isr()
905 * I2C transfer is terminated during the bus clear, so skip in tegra_i2c_isr()
908 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) in tegra_i2c_isr()
911 if (!i2c_dev->dma_mode) { in tegra_i2c_isr()
912 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
919 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; in tegra_i2c_isr()
924 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
925 if (i2c_dev->msg_buf_remaining) in tegra_i2c_isr()
934 if (i2c_dev->is_dvc) in tegra_i2c_isr()
943 * so forcing msg_buf_remaining to 0 in DMA mode. in tegra_i2c_isr()
946 if (i2c_dev->dma_mode) in tegra_i2c_isr()
947 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_isr()
952 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { in tegra_i2c_isr()
953 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
956 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
968 if (i2c_dev->hw->supports_bus_clear) in tegra_i2c_isr()
973 if (i2c_dev->is_dvc) in tegra_i2c_isr()
976 if (i2c_dev->dma_mode) { in tegra_i2c_isr()
977 if (i2c_dev->msg_read) in tegra_i2c_isr()
978 dmaengine_terminate_async(i2c_dev->rx_dma_chan); in tegra_i2c_isr()
980 dmaengine_terminate_async(i2c_dev->tx_dma_chan); in tegra_i2c_isr()
982 complete(&i2c_dev->dma_complete); in tegra_i2c_isr()
985 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
998 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1003 if (i2c_dev->dma_mode) { in tegra_i2c_config_fifo_trig()
1011 if (i2c_dev->msg_read) { in tegra_i2c_config_fifo_trig()
1012 chan = i2c_dev->rx_dma_chan; in tegra_i2c_config_fifo_trig()
1015 slv_config.src_addr = i2c_dev->base_phys + reg_offset; in tegra_i2c_config_fifo_trig()
1019 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1024 chan = i2c_dev->tx_dma_chan; in tegra_i2c_config_fifo_trig()
1027 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; in tegra_i2c_config_fifo_trig()
1031 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1040 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); in tegra_i2c_config_fifo_trig()
1041 dev_err(i2c_dev->dev, "falling back to PIO\n"); in tegra_i2c_config_fifo_trig()
1044 i2c_dev->dma_mode = false; in tegra_i2c_config_fifo_trig()
1050 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1071 tegra_i2c_isr(i2c_dev->irq, i2c_dev); in tegra_i2c_poll_completion()
1092 if (i2c_dev->atomic_mode) { in tegra_i2c_wait_completion()
1095 enable_irq(i2c_dev->irq); in tegra_i2c_wait_completion()
1098 disable_irq(i2c_dev->irq); in tegra_i2c_wait_completion()
1104 * case we will get timeout if I2C transfer is running on in tegra_i2c_wait_completion()
1123 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_issue_bus_clear()
1137 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); in tegra_i2c_issue_bus_clear()
1141 dev_err(i2c_dev->dev, "failed to clear bus\n"); in tegra_i2c_issue_bus_clear()
1142 return -ETIMEDOUT; in tegra_i2c_issue_bus_clear()
1147 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); in tegra_i2c_issue_bus_clear()
1148 return -EIO; in tegra_i2c_issue_bus_clear()
1151 return -EAGAIN; in tegra_i2c_issue_bus_clear()
1158 u32 *dma_buf = i2c_dev->dma_buf; in tegra_i2c_push_packet_header()
1164 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | in tegra_i2c_push_packet_header()
1167 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1172 packet_header = msg->len - 1; in tegra_i2c_push_packet_header()
1174 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1186 if (msg->flags & I2C_M_TEN) { in tegra_i2c_push_packet_header()
1187 packet_header |= msg->addr; in tegra_i2c_push_packet_header()
1190 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; in tegra_i2c_push_packet_header()
1193 if (msg->flags & I2C_M_IGNORE_NAK) in tegra_i2c_push_packet_header()
1196 if (msg->flags & I2C_M_RD) in tegra_i2c_push_packet_header()
1199 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1208 if (i2c_dev->msg_err == I2C_ERR_NONE) in tegra_i2c_error_recover()
1213 /* start recovery upon arbitration loss in single master mode */ in tegra_i2c_error_recover()
1214 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { in tegra_i2c_error_recover()
1215 if (!i2c_dev->multimaster_mode) in tegra_i2c_error_recover()
1216 return i2c_recover_bus(&i2c_dev->adapter); in tegra_i2c_error_recover()
1218 return -EAGAIN; in tegra_i2c_error_recover()
1221 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { in tegra_i2c_error_recover()
1222 if (msg->flags & I2C_M_IGNORE_NAK) in tegra_i2c_error_recover()
1225 return -EREMOTEIO; in tegra_i2c_error_recover()
1228 return -EIO; in tegra_i2c_error_recover()
1244 i2c_dev->msg_buf = msg->buf; in tegra_i2c_xfer_msg()
1247 if (msg->flags & I2C_M_RECV_LEN && end_state != MSG_END_CONTINUE) in tegra_i2c_xfer_msg()
1248 i2c_dev->msg_buf = msg->buf + 1; in tegra_i2c_xfer_msg()
1250 i2c_dev->msg_buf_remaining = msg->len; in tegra_i2c_xfer_msg()
1251 i2c_dev->msg_err = I2C_ERR_NONE; in tegra_i2c_xfer_msg()
1252 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); in tegra_i2c_xfer_msg()
1253 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_xfer_msg()
1255 if (i2c_dev->msg_read) in tegra_i2c_xfer_msg()
1256 xfer_size = msg->len; in tegra_i2c_xfer_msg()
1258 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE; in tegra_i2c_xfer_msg()
1262 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && in tegra_i2c_xfer_msg()
1263 i2c_dev->dma_buf && !i2c_dev->atomic_mode; in tegra_i2c_xfer_msg()
1272 i2c_dev->timings.bus_freq_hz); in tegra_i2c_xfer_msg()
1277 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1278 if (i2c_dev->msg_read) { in tegra_i2c_xfer_msg()
1279 dma_sync_single_for_device(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1280 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1287 dma_sync_single_for_cpu(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1288 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1295 if (!i2c_dev->msg_read) { in tegra_i2c_xfer_msg()
1296 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1297 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, in tegra_i2c_xfer_msg()
1298 msg->buf, msg->len); in tegra_i2c_xfer_msg()
1300 dma_sync_single_for_device(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1301 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1312 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) in tegra_i2c_xfer_msg()
1315 if (!i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1316 if (msg->flags & I2C_M_RD) in tegra_i2c_xfer_msg()
1318 else if (i2c_dev->msg_buf_remaining) in tegra_i2c_xfer_msg()
1323 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", in tegra_i2c_xfer_msg()
1326 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1328 &i2c_dev->dma_complete, in tegra_i2c_xfer_msg()
1336 dmaengine_synchronize(i2c_dev->msg_read ? in tegra_i2c_xfer_msg()
1337 i2c_dev->rx_dma_chan : in tegra_i2c_xfer_msg()
1338 i2c_dev->tx_dma_chan); in tegra_i2c_xfer_msg()
1340 dmaengine_terminate_sync(i2c_dev->msg_read ? in tegra_i2c_xfer_msg()
1341 i2c_dev->rx_dma_chan : in tegra_i2c_xfer_msg()
1342 i2c_dev->tx_dma_chan); in tegra_i2c_xfer_msg()
1344 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { in tegra_i2c_xfer_msg()
1345 dev_err(i2c_dev->dev, "DMA transfer timed out\n"); in tegra_i2c_xfer_msg()
1347 return -ETIMEDOUT; in tegra_i2c_xfer_msg()
1350 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { in tegra_i2c_xfer_msg()
1351 dma_sync_single_for_cpu(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1352 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1355 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len); in tegra_i2c_xfer_msg()
1359 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, in tegra_i2c_xfer_msg()
1365 dev_err(i2c_dev->dev, "I2C transfer timed out\n"); in tegra_i2c_xfer_msg()
1367 return -ETIMEDOUT; in tegra_i2c_xfer_msg()
1370 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", in tegra_i2c_xfer_msg()
1371 time_left, completion_done(&i2c_dev->msg_complete), in tegra_i2c_xfer_msg()
1372 i2c_dev->msg_err); in tegra_i2c_xfer_msg()
1374 i2c_dev->dma_mode = false; in tegra_i2c_xfer_msg()
1389 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_xfer()
1391 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); in tegra_i2c_xfer()
1392 pm_runtime_put_noidle(i2c_dev->dev); in tegra_i2c_xfer()
1399 if (i < (num - 1)) { in tegra_i2c_xfer()
1413 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len); in tegra_i2c_xfer()
1420 pm_runtime_put(i2c_dev->dev); in tegra_i2c_xfer()
1431 i2c_dev->atomic_mode = true; in tegra_i2c_xfer_atomic()
1433 i2c_dev->atomic_mode = false; in tegra_i2c_xfer_atomic()
1444 if (i2c_dev->hw->has_continue_xfer_support) in tegra_i2c_func()
1460 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1465 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1641 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1642 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1643 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1644 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1645 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1646 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1647 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1648 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1649 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1656 struct device_node *np = i2c_dev->dev->of_node; in tegra_i2c_parse_dt()
1659 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); in tegra_i2c_parse_dt()
1661 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); in tegra_i2c_parse_dt()
1662 i2c_dev->multimaster_mode = multi_mode; in tegra_i2c_parse_dt()
1664 if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) in tegra_i2c_parse_dt()
1665 i2c_dev->is_dvc = true; in tegra_i2c_parse_dt()
1667 if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) in tegra_i2c_parse_dt()
1668 i2c_dev->is_vi = true; in tegra_i2c_parse_dt()
1673 if (ACPI_HANDLE(i2c_dev->dev)) in tegra_i2c_init_reset()
1676 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); in tegra_i2c_init_reset()
1677 if (IS_ERR(i2c_dev->rst)) in tegra_i2c_init_reset()
1678 return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), in tegra_i2c_init_reset()
1688 if (ACPI_HANDLE(i2c_dev->dev)) in tegra_i2c_init_clocks()
1691 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; in tegra_i2c_init_clocks()
1693 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) in tegra_i2c_init_clocks()
1694 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; in tegra_i2c_init_clocks()
1696 if (i2c_dev->is_vi) in tegra_i2c_init_clocks()
1697 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; in tegra_i2c_init_clocks()
1699 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, in tegra_i2c_init_clocks()
1700 i2c_dev->clocks); in tegra_i2c_init_clocks()
1704 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_init_clocks()
1708 i2c_dev->div_clk = i2c_dev->clocks[0].clk; in tegra_i2c_init_clocks()
1710 if (!i2c_dev->multimaster_mode) in tegra_i2c_init_clocks()
1713 err = clk_enable(i2c_dev->div_clk); in tegra_i2c_init_clocks()
1715 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); in tegra_i2c_init_clocks()
1722 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_init_clocks()
1729 if (i2c_dev->multimaster_mode) in tegra_i2c_release_clocks()
1730 clk_disable(i2c_dev->div_clk); in tegra_i2c_release_clocks()
1732 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_release_clocks()
1739 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_init_hardware()
1741 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); in tegra_i2c_init_hardware()
1745 pm_runtime_put_sync(i2c_dev->dev); in tegra_i2c_init_hardware()
1756 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in tegra_i2c_probe()
1758 return -ENOMEM; in tegra_i2c_probe()
1762 init_completion(&i2c_dev->msg_complete); in tegra_i2c_probe()
1763 init_completion(&i2c_dev->dma_complete); in tegra_i2c_probe()
1765 i2c_dev->hw = device_get_match_data(&pdev->dev); in tegra_i2c_probe()
1766 i2c_dev->cont_id = pdev->id; in tegra_i2c_probe()
1767 i2c_dev->dev = &pdev->dev; in tegra_i2c_probe()
1769 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in tegra_i2c_probe()
1770 if (IS_ERR(i2c_dev->base)) in tegra_i2c_probe()
1771 return PTR_ERR(i2c_dev->base); in tegra_i2c_probe()
1773 i2c_dev->base_phys = res->start; in tegra_i2c_probe()
1779 i2c_dev->irq = err; in tegra_i2c_probe()
1782 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); in tegra_i2c_probe()
1784 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq, in tegra_i2c_probe()
1787 dev_name(i2c_dev->dev), i2c_dev); in tegra_i2c_probe()
1806 * VI I2C is in VE power domain which is not always ON and not in tegra_i2c_probe()
1807 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a in tegra_i2c_probe()
1808 * non IRQ-safe domain because this prevents powering off the power in tegra_i2c_probe()
1811 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't in tegra_i2c_probe()
1814 if (!i2c_dev->is_vi) in tegra_i2c_probe()
1815 pm_runtime_irq_safe(i2c_dev->dev); in tegra_i2c_probe()
1817 pm_runtime_enable(i2c_dev->dev); in tegra_i2c_probe()
1823 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); in tegra_i2c_probe()
1824 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; in tegra_i2c_probe()
1825 i2c_dev->adapter.dev.parent = i2c_dev->dev; in tegra_i2c_probe()
1826 i2c_dev->adapter.retries = 1; in tegra_i2c_probe()
1827 i2c_dev->adapter.timeout = 6 * HZ; in tegra_i2c_probe()
1828 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; in tegra_i2c_probe()
1829 i2c_dev->adapter.owner = THIS_MODULE; in tegra_i2c_probe()
1830 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; in tegra_i2c_probe()
1831 i2c_dev->adapter.algo = &tegra_i2c_algo; in tegra_i2c_probe()
1832 i2c_dev->adapter.nr = pdev->id; in tegra_i2c_probe()
1834 if (i2c_dev->hw->supports_bus_clear) in tegra_i2c_probe()
1835 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; in tegra_i2c_probe()
1837 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), in tegra_i2c_probe()
1838 sizeof(i2c_dev->adapter.name)); in tegra_i2c_probe()
1840 err = i2c_add_numbered_adapter(&i2c_dev->adapter); in tegra_i2c_probe()
1847 pm_runtime_disable(i2c_dev->dev); in tegra_i2c_probe()
1860 i2c_del_adapter(&i2c_dev->adapter); in tegra_i2c_remove()
1861 pm_runtime_force_suspend(i2c_dev->dev); in tegra_i2c_remove()
1878 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_resume()
1883 * VI I2C device is attached to VE power domain which goes through in tegra_i2c_runtime_resume()
1885 * controller needs to be re-initialized after power ON. in tegra_i2c_runtime_resume()
1887 if (i2c_dev->is_vi) { in tegra_i2c_runtime_resume()
1896 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_resume()
1905 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_suspend()
1915 i2c_mark_adapter_suspended(&i2c_dev->adapter); in tegra_i2c_suspend()
1954 i2c_mark_adapter_resumed(&i2c_dev->adapter); in tegra_i2c_resume()
1977 .name = "tegra-i2c",
1985 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");