41 #define STM32F7_I2C_CR1				0x00  macro
431 	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_disable_irq()
723 	stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_disable_dma_req()
752 		stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
755 		stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
759 	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
761 	stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
764 	stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
841 	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_release_bus()
880 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);  in stm32f7_i2c_xfer_msg()
948 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);  in stm32f7_i2c_xfer_msg()
966 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_xfer_msg()
1114 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_xfer_msg()
1128 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_rep_start()
1198 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_rep_start()
1282 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_slave_start()
1287 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_slave_start()
1307 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_slave_start()
1831 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_enable_wakeup()
1834 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_enable_wakeup()
1915 	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_reg_slave()
2026 	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);  in stm32f7_i2c_enable_smbus_host()
2037 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,  in stm32f7_i2c_disable_smbus_host()
2061 	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);  in stm32f7_i2c_enable_smbus_alert()
2073 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,  in stm32f7_i2c_disable_smbus_alert()
2383 	backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);  in stm32f7_i2c_regs_backup()
2405 	cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);  in stm32f7_i2c_regs_restore()
2407 		stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_regs_restore()
2412 		       i2c_dev->base + STM32F7_I2C_CR1);  in stm32f7_i2c_regs_restore()
2414 		stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_regs_restore()