Lines Matching +full:i2c +full:- +full:sda +full:- +full:hold +full:- +full:time +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics STM32F7 I2C controller
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
14 * This driver is based on i2c-stm32f4.c
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
38 #include "i2c-stm32.h"
40 /* STM32F7 I2C registers */
52 /* STM32F7 I2C control 1 */
83 /* STM32F7 I2C control 2 */
100 /* STM32F7 I2C Own Address 1 */
113 /* STM32F7 I2C Own Address 2 */
123 /* STM32F7 I2C Interrupt Status */
142 /* STM32F7 I2C Interrupt Clear */
151 /* STM32F7 I2C Timing */
170 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
173 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
174 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
185 * struct stm32f7_i2c_regs - i2c f7 registers backup
201 * struct stm32f7_i2c_spec - private i2c specification timing
202 * @rate: I2C bus speed (Hz)
203 * @fall_max: Max fall time of both SDA and SCL signals (ns)
204 * @rise_max: Max rise time of both SDA and SCL signals (ns)
205 * @hddat_min: Min data hold time (ns)
206 * @vddat_max: Max data valid time (ns)
207 * @sudat_min: Min data setup time (ns)
208 * @l_min: Min low period of the SCL clock (ns)
209 * @h_min: Min high period of the SCL clock (ns)
223 * struct stm32f7_i2c_setup - private I2C timing setup parameters
224 * @speed_freq: I2C speed frequency (Hz)
225 * @clock_src: I2C clock source frequency (Hz)
226 * @rise_time: Rise time (ns)
227 * @fall_time: Fall time (ns)
239 * struct stm32f7_i2c_timings - private I2C output parameters
242 * @scldel: Data setup time
243 * @sdadel: Data hold time
257 * struct stm32f7_i2c_msg - client specific data
258 * @addr: 8-bit or 10-bit slave addr, including r/w bit
262 * @stop: last I2C msg to be sent, i.e. STOP to be generated
263 * @smbus: boolean to know if the I2C IP is used in SMBus mode
266 * SMBus block read and SMBus block write - block read process call protocols
269 * This buffer has to be 32-bit aligned to be compliant with memory address
285 * struct stm32f7_i2c_alert - SMBus alert specific data
286 * @setup: platform data for the smbus_alert i2c client
287 * @ara: I2C slave device used to respond to the SMBus Alert with Alert
296 * struct stm32f7_i2c_dev - private data of the controller
297 * @adap: I2C adapter for this controller
300 * @complete: completion of I2C message
301 * @clk: hw i2c clock
302 * @bus_rate: I2C clock frequency of the controller
304 * @msg_num: number of I2C messages to be executed
306 * @f7_msg: customized i2c msg for driver usage
307 * @setup: I2C timing input setup
308 * @timing: I2C computed timings
309 * @slave: list of slave devices registered on the I2C bus
311 * @backup_regs: backup of i2c controller registers (for suspend/resume)
313 * @master_mode: boolean to know in which mode the I2C is running (master or
323 * @host_notify_client: SMBus host-notify client
363 * All these values are coming from I2C Specification, Version 6.0, 4th of
366 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
367 * and Fast-mode Plus I2C-bus devices
431 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_disable_irq()
442 return ERR_PTR(-EINVAL); in stm32f7_get_specs()
453 setup->clock_src); in stm32f7_i2c_compute_timing()
455 setup->speed_freq); in stm32f7_i2c_compute_timing()
468 specs = stm32f7_get_specs(setup->speed_freq); in stm32f7_i2c_compute_timing()
469 if (specs == ERR_PTR(-EINVAL)) { in stm32f7_i2c_compute_timing()
470 dev_err(i2c_dev->dev, "speed out of bound {%d}\n", in stm32f7_i2c_compute_timing()
471 setup->speed_freq); in stm32f7_i2c_compute_timing()
472 return -EINVAL; in stm32f7_i2c_compute_timing()
475 if ((setup->rise_time > specs->rise_max) || in stm32f7_i2c_compute_timing()
476 (setup->fall_time > specs->fall_max)) { in stm32f7_i2c_compute_timing()
477 dev_err(i2c_dev->dev, in stm32f7_i2c_compute_timing()
479 setup->rise_time, specs->rise_max, in stm32f7_i2c_compute_timing()
480 setup->fall_time, specs->fall_max); in stm32f7_i2c_compute_timing()
481 return -EINVAL; in stm32f7_i2c_compute_timing()
484 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); in stm32f7_i2c_compute_timing()
485 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) { in stm32f7_i2c_compute_timing()
486 dev_err(i2c_dev->dev, in stm32f7_i2c_compute_timing()
488 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk); in stm32f7_i2c_compute_timing()
489 return -EINVAL; in stm32f7_i2c_compute_timing()
494 (i2c_dev->analog_filter ? in stm32f7_i2c_compute_timing()
497 (i2c_dev->analog_filter ? in stm32f7_i2c_compute_timing()
499 dnf_delay = i2c_dev->dnf * i2cclk; in stm32f7_i2c_compute_timing()
501 sdadel_min = specs->hddat_min + setup->fall_time - in stm32f7_i2c_compute_timing()
502 af_delay_min - (i2c_dev->dnf + 3) * i2cclk; in stm32f7_i2c_compute_timing()
504 sdadel_max = specs->vddat_max - setup->rise_time - in stm32f7_i2c_compute_timing()
505 af_delay_max - (i2c_dev->dnf + 4) * i2cclk; in stm32f7_i2c_compute_timing()
507 scldel_min = setup->rise_time + specs->sudat_min; in stm32f7_i2c_compute_timing()
514 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", in stm32f7_i2c_compute_timing()
534 ret = -ENOMEM; in stm32f7_i2c_compute_timing()
538 v->presc = p; in stm32f7_i2c_compute_timing()
539 v->scldel = l; in stm32f7_i2c_compute_timing()
540 v->sdadel = a; in stm32f7_i2c_compute_timing()
543 list_add_tail(&v->node, in stm32f7_i2c_compute_timing()
555 dev_err(i2c_dev->dev, "no Prescaler solution\n"); in stm32f7_i2c_compute_timing()
556 ret = -EPERM; in stm32f7_i2c_compute_timing()
562 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); in stm32f7_i2c_compute_timing()
563 clk_min = NSEC_PER_SEC / setup->speed_freq; in stm32f7_i2c_compute_timing()
568 * - SCL Low Period has to be higher than SCL Clock Low Period in stm32f7_i2c_compute_timing()
569 * defined by I2C Specification. I2C Clock has to be lower than in stm32f7_i2c_compute_timing()
570 * (SCL Low Period - Analog/Digital filters) / 4. in stm32f7_i2c_compute_timing()
571 * - SCL High Period has to be lower than SCL Clock High Period in stm32f7_i2c_compute_timing()
572 * defined by I2C Specification in stm32f7_i2c_compute_timing()
573 * - I2C Clock has to be lower than SCL High Period in stm32f7_i2c_compute_timing()
576 u32 prescaler = (v->presc + 1) * i2cclk; in stm32f7_i2c_compute_timing()
581 if ((tscl_l < specs->l_min) || in stm32f7_i2c_compute_timing()
583 ((tscl_l - af_delay_min - dnf_delay) / 4))) { in stm32f7_i2c_compute_timing()
590 setup->rise_time + setup->fall_time; in stm32f7_i2c_compute_timing()
593 (tscl_h >= specs->h_min) && in stm32f7_i2c_compute_timing()
595 int clk_error = tscl - i2cbus; in stm32f7_i2c_compute_timing()
598 clk_error = -clk_error; in stm32f7_i2c_compute_timing()
602 v->scll = l; in stm32f7_i2c_compute_timing()
603 v->sclh = h; in stm32f7_i2c_compute_timing()
612 dev_err(i2c_dev->dev, "no solution at all\n"); in stm32f7_i2c_compute_timing()
613 ret = -EPERM; in stm32f7_i2c_compute_timing()
617 output->presc = s->presc; in stm32f7_i2c_compute_timing()
618 output->scldel = s->scldel; in stm32f7_i2c_compute_timing()
619 output->sdadel = s->sdadel; in stm32f7_i2c_compute_timing()
620 output->scll = s->scll; in stm32f7_i2c_compute_timing()
621 output->sclh = s->sclh; in stm32f7_i2c_compute_timing()
623 dev_dbg(i2c_dev->dev, in stm32f7_i2c_compute_timing()
625 output->presc, in stm32f7_i2c_compute_timing()
626 output->scldel, output->sdadel, in stm32f7_i2c_compute_timing()
627 output->scll, output->sclh); in stm32f7_i2c_compute_timing()
632 list_del(&v->node); in stm32f7_i2c_compute_timing()
643 while (--i) in stm32f7_get_lower_rate()
656 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; in stm32f7_i2c_setup_timing()
657 t->scl_rise_ns = i2c_dev->setup.rise_time; in stm32f7_i2c_setup_timing()
658 t->scl_fall_ns = i2c_dev->setup.fall_time; in stm32f7_i2c_setup_timing()
660 i2c_parse_fw_timings(i2c_dev->dev, t, false); in stm32f7_i2c_setup_timing()
662 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { in stm32f7_i2c_setup_timing()
663 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n", in stm32f7_i2c_setup_timing()
664 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); in stm32f7_i2c_setup_timing()
665 return -EINVAL; in stm32f7_i2c_setup_timing()
668 setup->speed_freq = t->bus_freq_hz; in stm32f7_i2c_setup_timing()
669 i2c_dev->setup.rise_time = t->scl_rise_ns; in stm32f7_i2c_setup_timing()
670 i2c_dev->setup.fall_time = t->scl_fall_ns; in stm32f7_i2c_setup_timing()
671 i2c_dev->dnf_dt = t->digital_filter_width_ns; in stm32f7_i2c_setup_timing()
672 setup->clock_src = clk_get_rate(i2c_dev->clk); in stm32f7_i2c_setup_timing()
674 if (!setup->clock_src) { in stm32f7_i2c_setup_timing()
675 dev_err(i2c_dev->dev, "clock rate is 0\n"); in stm32f7_i2c_setup_timing()
676 return -EINVAL; in stm32f7_i2c_setup_timing()
679 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) in stm32f7_i2c_setup_timing()
680 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; in stm32f7_i2c_setup_timing()
684 &i2c_dev->timing); in stm32f7_i2c_setup_timing()
686 dev_err(i2c_dev->dev, in stm32f7_i2c_setup_timing()
687 "failed to compute I2C timings.\n"); in stm32f7_i2c_setup_timing()
688 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) in stm32f7_i2c_setup_timing()
690 setup->speed_freq = in stm32f7_i2c_setup_timing()
691 stm32f7_get_lower_rate(setup->speed_freq); in stm32f7_i2c_setup_timing()
692 dev_warn(i2c_dev->dev, in stm32f7_i2c_setup_timing()
693 "downgrade I2C Speed Freq to (%i)\n", in stm32f7_i2c_setup_timing()
694 setup->speed_freq); in stm32f7_i2c_setup_timing()
699 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); in stm32f7_i2c_setup_timing()
703 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, in stm32f7_i2c_setup_timing()
704 "i2c-analog-filter"); in stm32f7_i2c_setup_timing()
706 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", in stm32f7_i2c_setup_timing()
707 setup->speed_freq, setup->clock_src); in stm32f7_i2c_setup_timing()
708 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", in stm32f7_i2c_setup_timing()
709 setup->rise_time, setup->fall_time); in stm32f7_i2c_setup_timing()
710 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", in stm32f7_i2c_setup_timing()
711 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf); in stm32f7_i2c_setup_timing()
713 i2c_dev->bus_rate = setup->speed_freq; in stm32f7_i2c_setup_timing()
720 void __iomem *base = i2c_dev->base; in stm32f7_i2c_disable_dma_req()
729 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_dma_callback()
730 struct device *dev = dma->chan_using->device->dev; in stm32f7_i2c_dma_callback()
733 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); in stm32f7_i2c_dma_callback()
734 complete(&dma->dma_complete); in stm32f7_i2c_dma_callback()
739 struct stm32f7_i2c_timings *t = &i2c_dev->timing; in stm32f7_i2c_hw_config()
743 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); in stm32f7_i2c_hw_config()
744 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); in stm32f7_i2c_hw_config()
745 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); in stm32f7_i2c_hw_config()
746 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); in stm32f7_i2c_hw_config()
747 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); in stm32f7_i2c_hw_config()
748 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); in stm32f7_i2c_hw_config()
751 if (i2c_dev->analog_filter) in stm32f7_i2c_hw_config()
752 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
755 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
759 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
761 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
762 STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); in stm32f7_i2c_hw_config()
764 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
770 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_write_tx_data()
771 void __iomem *base = i2c_dev->base; in stm32f7_i2c_write_tx_data()
773 if (f7_msg->count) { in stm32f7_i2c_write_tx_data()
774 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); in stm32f7_i2c_write_tx_data()
775 f7_msg->count--; in stm32f7_i2c_write_tx_data()
781 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_read_rx_data()
782 void __iomem *base = i2c_dev->base; in stm32f7_i2c_read_rx_data()
784 if (f7_msg->count) { in stm32f7_i2c_read_rx_data()
785 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); in stm32f7_i2c_read_rx_data()
786 f7_msg->count--; in stm32f7_i2c_read_rx_data()
795 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_reload()
798 if (i2c_dev->use_dma) in stm32f7_i2c_reload()
799 f7_msg->count -= STM32F7_I2C_MAX_LEN; in stm32f7_i2c_reload()
801 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_reload()
804 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { in stm32f7_i2c_reload()
808 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_reload()
811 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_reload()
816 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_reload()
829 val = f7_msg->buf - sizeof(u8); in stm32f7_i2c_smbus_reload()
830 f7_msg->count = *val; in stm32f7_i2c_smbus_reload()
831 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_smbus_reload()
833 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_reload()
834 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_smbus_reload()
841 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_release_bus()
852 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, in stm32f7_i2c_wait_free_bus()
859 stm32f7_i2c_release_bus(&i2c_dev->adap); in stm32f7_i2c_wait_free_bus()
861 return -EBUSY; in stm32f7_i2c_wait_free_bus()
867 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_xfer_msg()
868 void __iomem *base = i2c_dev->base; in stm32f7_i2c_xfer_msg()
872 f7_msg->addr = msg->addr; in stm32f7_i2c_xfer_msg()
873 f7_msg->buf = msg->buf; in stm32f7_i2c_xfer_msg()
874 f7_msg->count = msg->len; in stm32f7_i2c_xfer_msg()
875 f7_msg->result = 0; in stm32f7_i2c_xfer_msg()
876 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); in stm32f7_i2c_xfer_msg()
878 reinit_completion(&i2c_dev->complete); in stm32f7_i2c_xfer_msg()
885 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
890 if (msg->flags & I2C_M_TEN) { in stm32f7_i2c_xfer_msg()
892 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); in stm32f7_i2c_xfer_msg()
896 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); in stm32f7_i2c_xfer_msg()
901 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { in stm32f7_i2c_xfer_msg()
905 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_xfer_msg()
917 i2c_dev->use_dma = false; in stm32f7_i2c_xfer_msg()
918 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { in stm32f7_i2c_xfer_msg()
919 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_xfer_msg()
920 msg->flags & I2C_M_RD, in stm32f7_i2c_xfer_msg()
921 f7_msg->count, f7_msg->buf, in stm32f7_i2c_xfer_msg()
925 i2c_dev->use_dma = true; in stm32f7_i2c_xfer_msg()
927 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_xfer_msg()
930 if (!i2c_dev->use_dma) { in stm32f7_i2c_xfer_msg()
931 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
936 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
945 i2c_dev->master_mode = true; in stm32f7_i2c_xfer_msg()
956 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_xfer_msg()
957 struct device *dev = i2c_dev->dev; in stm32f7_i2c_smbus_xfer_msg()
958 void __iomem *base = i2c_dev->base; in stm32f7_i2c_smbus_xfer_msg()
962 f7_msg->result = 0; in stm32f7_i2c_smbus_xfer_msg()
963 reinit_completion(&i2c_dev->complete); in stm32f7_i2c_smbus_xfer_msg()
970 if (f7_msg->read_write) in stm32f7_i2c_smbus_xfer_msg()
975 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); in stm32f7_i2c_smbus_xfer_msg()
977 f7_msg->smbus_buf[0] = command; in stm32f7_i2c_smbus_xfer_msg()
978 switch (f7_msg->size) { in stm32f7_i2c_smbus_xfer_msg()
980 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
981 f7_msg->count = 0; in stm32f7_i2c_smbus_xfer_msg()
984 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
985 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
988 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
989 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
990 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
993 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
994 f7_msg->count = 2; in stm32f7_i2c_smbus_xfer_msg()
995 f7_msg->smbus_buf[1] = data->byte; in stm32f7_i2c_smbus_xfer_msg()
999 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
1000 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1001 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
1004 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
1005 f7_msg->count = 3; in stm32f7_i2c_smbus_xfer_msg()
1006 f7_msg->smbus_buf[1] = data->word & 0xff; in stm32f7_i2c_smbus_xfer_msg()
1007 f7_msg->smbus_buf[2] = data->word >> 8; in stm32f7_i2c_smbus_xfer_msg()
1011 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
1012 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1013 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
1016 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
1017 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || in stm32f7_i2c_smbus_xfer_msg()
1018 !data->block[0]) { in stm32f7_i2c_smbus_xfer_msg()
1020 data->block[0]); in stm32f7_i2c_smbus_xfer_msg()
1021 return -EINVAL; in stm32f7_i2c_smbus_xfer_msg()
1023 f7_msg->count = data->block[0] + 2; in stm32f7_i2c_smbus_xfer_msg()
1024 for (i = 1; i < f7_msg->count; i++) in stm32f7_i2c_smbus_xfer_msg()
1025 f7_msg->smbus_buf[i] = data->block[i - 1]; in stm32f7_i2c_smbus_xfer_msg()
1029 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1030 f7_msg->count = 3; in stm32f7_i2c_smbus_xfer_msg()
1031 f7_msg->smbus_buf[1] = data->word & 0xff; in stm32f7_i2c_smbus_xfer_msg()
1032 f7_msg->smbus_buf[2] = data->word >> 8; in stm32f7_i2c_smbus_xfer_msg()
1034 f7_msg->read_write = I2C_SMBUS_READ; in stm32f7_i2c_smbus_xfer_msg()
1037 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1038 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { in stm32f7_i2c_smbus_xfer_msg()
1040 data->block[0]); in stm32f7_i2c_smbus_xfer_msg()
1041 return -EINVAL; in stm32f7_i2c_smbus_xfer_msg()
1043 f7_msg->count = data->block[0] + 2; in stm32f7_i2c_smbus_xfer_msg()
1044 for (i = 1; i < f7_msg->count; i++) in stm32f7_i2c_smbus_xfer_msg()
1045 f7_msg->smbus_buf[i] = data->block[i - 1]; in stm32f7_i2c_smbus_xfer_msg()
1047 f7_msg->read_write = I2C_SMBUS_READ; in stm32f7_i2c_smbus_xfer_msg()
1050 /* Rely on emulated i2c transfer (through master_xfer) */ in stm32f7_i2c_smbus_xfer_msg()
1051 return -EOPNOTSUPP; in stm32f7_i2c_smbus_xfer_msg()
1053 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); in stm32f7_i2c_smbus_xfer_msg()
1054 return -EOPNOTSUPP; in stm32f7_i2c_smbus_xfer_msg()
1057 f7_msg->buf = f7_msg->smbus_buf; in stm32f7_i2c_smbus_xfer_msg()
1060 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { in stm32f7_i2c_smbus_xfer_msg()
1063 if (!f7_msg->read_write) in stm32f7_i2c_smbus_xfer_msg()
1064 f7_msg->count++; in stm32f7_i2c_smbus_xfer_msg()
1072 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_xfer_msg()
1083 i2c_dev->use_dma = false; in stm32f7_i2c_smbus_xfer_msg()
1084 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { in stm32f7_i2c_smbus_xfer_msg()
1085 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_smbus_xfer_msg()
1087 f7_msg->count, f7_msg->buf, in stm32f7_i2c_smbus_xfer_msg()
1091 i2c_dev->use_dma = true; in stm32f7_i2c_smbus_xfer_msg()
1093 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_smbus_xfer_msg()
1096 if (!i2c_dev->use_dma) { in stm32f7_i2c_smbus_xfer_msg()
1111 i2c_dev->master_mode = true; in stm32f7_i2c_smbus_xfer_msg()
1122 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_rep_start()
1123 void __iomem *base = i2c_dev->base; in stm32f7_i2c_smbus_rep_start()
1133 switch (f7_msg->size) { in stm32f7_i2c_smbus_rep_start()
1135 f7_msg->count = 1; in stm32f7_i2c_smbus_rep_start()
1139 f7_msg->count = 2; in stm32f7_i2c_smbus_rep_start()
1143 f7_msg->count = 1; in stm32f7_i2c_smbus_rep_start()
1148 f7_msg->buf = f7_msg->smbus_buf; in stm32f7_i2c_smbus_rep_start()
1149 f7_msg->stop = true; in stm32f7_i2c_smbus_rep_start()
1153 f7_msg->count++; in stm32f7_i2c_smbus_rep_start()
1157 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_rep_start()
1173 i2c_dev->use_dma = false; in stm32f7_i2c_smbus_rep_start()
1174 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && in stm32f7_i2c_smbus_rep_start()
1175 f7_msg->size != I2C_SMBUS_BLOCK_DATA && in stm32f7_i2c_smbus_rep_start()
1176 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { in stm32f7_i2c_smbus_rep_start()
1177 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_smbus_rep_start()
1179 f7_msg->count, f7_msg->buf, in stm32f7_i2c_smbus_rep_start()
1184 i2c_dev->use_dma = true; in stm32f7_i2c_smbus_rep_start()
1186 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_smbus_rep_start()
1189 if (!i2c_dev->use_dma) in stm32f7_i2c_smbus_rep_start()
1204 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_check_pec()
1207 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); in stm32f7_i2c_smbus_check_pec()
1209 switch (f7_msg->size) { in stm32f7_i2c_smbus_check_pec()
1212 received_pec = f7_msg->smbus_buf[1]; in stm32f7_i2c_smbus_check_pec()
1216 received_pec = f7_msg->smbus_buf[2]; in stm32f7_i2c_smbus_check_pec()
1220 count = f7_msg->smbus_buf[0]; in stm32f7_i2c_smbus_check_pec()
1221 received_pec = f7_msg->smbus_buf[count]; in stm32f7_i2c_smbus_check_pec()
1224 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); in stm32f7_i2c_smbus_check_pec()
1225 return -EINVAL; in stm32f7_i2c_smbus_check_pec()
1229 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", in stm32f7_i2c_smbus_check_pec()
1231 return -EBADMSG; in stm32f7_i2c_smbus_check_pec()
1244 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_is_addr_match()
1246 * For 10-bit addr, addcode = 11110XY with in stm32f7_i2c_is_addr_match()
1250 addr = slave->addr >> 8; in stm32f7_i2c_is_addr_match()
1255 addr = slave->addr & 0x7f; in stm32f7_i2c_is_addr_match()
1265 struct i2c_client *slave = i2c_dev->slave_running; in stm32f7_i2c_slave_start()
1266 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_start()
1270 if (i2c_dev->slave_dir) { in stm32f7_i2c_slave_start()
1271 /* Notify i2c slave that new read transfer is starting */ in stm32f7_i2c_slave_start()
1275 * Disable slave TX config in case of I2C combined message in stm32f7_i2c_slave_start()
1276 * (I2C Write followed by I2C Read) in stm32f7_i2c_slave_start()
1292 /* Notify i2c slave that new write transfer is starting */ in stm32f7_i2c_slave_start()
1313 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_addr()
1317 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_slave_addr()
1322 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { in stm32f7_i2c_slave_addr()
1323 i2c_dev->slave_running = i2c_dev->slave[i]; in stm32f7_i2c_slave_addr()
1324 i2c_dev->slave_dir = dir; in stm32f7_i2c_slave_addr()
1326 /* Start I2C slave processing */ in stm32f7_i2c_slave_addr()
1343 if (i2c_dev->slave[i] == slave) { in stm32f7_i2c_get_slave_id()
1349 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); in stm32f7_i2c_get_slave_id()
1351 return -ENODEV; in stm32f7_i2c_get_slave_id()
1357 struct device *dev = i2c_dev->dev; in stm32f7_i2c_get_free_slave_id()
1362 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address in stm32f7_i2c_get_free_slave_id()
1363 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only in stm32f7_i2c_get_free_slave_id()
1365 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) { in stm32f7_i2c_get_free_slave_id()
1366 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY]) in stm32f7_i2c_get_free_slave_id()
1372 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) { in stm32f7_i2c_get_free_slave_id()
1374 (slave->flags & I2C_CLIENT_TEN)) in stm32f7_i2c_get_free_slave_id()
1376 if (!i2c_dev->slave[i]) { in stm32f7_i2c_get_free_slave_id()
1383 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); in stm32f7_i2c_get_free_slave_id()
1385 return -EINVAL; in stm32f7_i2c_get_free_slave_id()
1393 if (i2c_dev->slave[i]) in stm32f7_i2c_is_slave_registered()
1406 if (i2c_dev->slave[i]) in stm32f7_i2c_is_slave_busy()
1415 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_isr_event()
1420 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_slave_isr_event()
1424 i2c_slave_event(i2c_dev->slave_running, in stm32f7_i2c_slave_isr_event()
1438 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); in stm32f7_i2c_slave_isr_event()
1439 ret = i2c_slave_event(i2c_dev->slave_running, in stm32f7_i2c_slave_isr_event()
1443 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_slave_isr_event()
1445 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_slave_isr_event()
1454 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); in stm32f7_i2c_slave_isr_event()
1463 if (i2c_dev->slave_dir) { in stm32f7_i2c_slave_isr_event()
1475 /* Notify i2c slave that a STOP flag has been detected */ in stm32f7_i2c_slave_isr_event()
1476 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); in stm32f7_i2c_slave_isr_event()
1478 i2c_dev->slave_running = NULL; in stm32f7_i2c_slave_isr_event()
1491 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_isr_event()
1492 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_isr_event()
1493 void __iomem *base = i2c_dev->base; in stm32f7_i2c_isr_event()
1498 if (!i2c_dev->master_mode) { in stm32f7_i2c_isr_event()
1503 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_event()
1515 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", in stm32f7_i2c_isr_event()
1516 __func__, f7_msg->addr); in stm32f7_i2c_isr_event()
1518 if (i2c_dev->use_dma) { in stm32f7_i2c_isr_event()
1520 dmaengine_terminate_async(dma->chan_using); in stm32f7_i2c_isr_event()
1522 f7_msg->result = -ENXIO; in stm32f7_i2c_isr_event()
1537 if (i2c_dev->use_dma && !f7_msg->result) { in stm32f7_i2c_isr_event()
1540 i2c_dev->master_mode = false; in stm32f7_i2c_isr_event()
1541 complete(&i2c_dev->complete); in stm32f7_i2c_isr_event()
1547 if (f7_msg->stop) { in stm32f7_i2c_isr_event()
1550 } else if (i2c_dev->use_dma && !f7_msg->result) { in stm32f7_i2c_isr_event()
1552 } else if (f7_msg->smbus) { in stm32f7_i2c_isr_event()
1555 i2c_dev->msg_id++; in stm32f7_i2c_isr_event()
1556 i2c_dev->msg++; in stm32f7_i2c_isr_event()
1557 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); in stm32f7_i2c_isr_event()
1562 if (f7_msg->smbus) in stm32f7_i2c_isr_event()
1574 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_isr_event_thread()
1575 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_isr_event_thread()
1583 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); in stm32f7_i2c_isr_event_thread()
1585 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); in stm32f7_i2c_isr_event_thread()
1587 dmaengine_terminate_async(dma->chan_using); in stm32f7_i2c_isr_event_thread()
1588 f7_msg->result = -ETIMEDOUT; in stm32f7_i2c_isr_event_thread()
1591 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_event_thread()
1594 if (f7_msg->smbus) { in stm32f7_i2c_isr_event_thread()
1597 i2c_dev->msg_id++; in stm32f7_i2c_isr_event_thread()
1598 i2c_dev->msg++; in stm32f7_i2c_isr_event_thread()
1599 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); in stm32f7_i2c_isr_event_thread()
1602 i2c_dev->master_mode = false; in stm32f7_i2c_isr_event_thread()
1603 complete(&i2c_dev->complete); in stm32f7_i2c_isr_event_thread()
1612 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_isr_error()
1613 void __iomem *base = i2c_dev->base; in stm32f7_i2c_isr_error()
1614 struct device *dev = i2c_dev->dev; in stm32f7_i2c_isr_error()
1615 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_isr_error()
1618 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_error()
1623 __func__, f7_msg->addr); in stm32f7_i2c_isr_error()
1625 stm32f7_i2c_release_bus(&i2c_dev->adap); in stm32f7_i2c_isr_error()
1626 f7_msg->result = -EIO; in stm32f7_i2c_isr_error()
1632 __func__, f7_msg->addr); in stm32f7_i2c_isr_error()
1634 f7_msg->result = -EAGAIN; in stm32f7_i2c_isr_error()
1639 __func__, f7_msg->addr); in stm32f7_i2c_isr_error()
1641 f7_msg->result = -EINVAL; in stm32f7_i2c_isr_error()
1647 i2c_handle_smbus_alert(i2c_dev->alert->ara); in stm32f7_i2c_isr_error()
1651 if (!i2c_dev->slave_running) { in stm32f7_i2c_isr_error()
1662 if (i2c_dev->use_dma) { in stm32f7_i2c_isr_error()
1664 dmaengine_terminate_async(dma->chan_using); in stm32f7_i2c_isr_error()
1667 i2c_dev->master_mode = false; in stm32f7_i2c_isr_error()
1668 complete(&i2c_dev->complete); in stm32f7_i2c_isr_error()
1677 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_xfer()
1678 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_xfer()
1682 i2c_dev->msg = msgs; in stm32f7_i2c_xfer()
1683 i2c_dev->msg_num = num; in stm32f7_i2c_xfer()
1684 i2c_dev->msg_id = 0; in stm32f7_i2c_xfer()
1685 f7_msg->smbus = false; in stm32f7_i2c_xfer()
1687 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_xfer()
1697 time_left = wait_for_completion_timeout(&i2c_dev->complete, in stm32f7_i2c_xfer()
1698 i2c_dev->adap.timeout); in stm32f7_i2c_xfer()
1699 ret = f7_msg->result; in stm32f7_i2c_xfer()
1701 if (i2c_dev->use_dma) in stm32f7_i2c_xfer()
1702 dmaengine_synchronize(dma->chan_using); in stm32f7_i2c_xfer()
1710 i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_xfer()
1715 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", in stm32f7_i2c_xfer()
1716 i2c_dev->msg->addr); in stm32f7_i2c_xfer()
1717 if (i2c_dev->use_dma) in stm32f7_i2c_xfer()
1718 dmaengine_terminate_sync(dma->chan_using); in stm32f7_i2c_xfer()
1720 ret = -ETIMEDOUT; in stm32f7_i2c_xfer()
1724 pm_runtime_mark_last_busy(i2c_dev->dev); in stm32f7_i2c_xfer()
1725 pm_runtime_put_autosuspend(i2c_dev->dev); in stm32f7_i2c_xfer()
1736 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_xfer()
1737 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_smbus_xfer()
1738 struct device *dev = i2c_dev->dev; in stm32f7_i2c_smbus_xfer()
1742 f7_msg->addr = addr; in stm32f7_i2c_smbus_xfer()
1743 f7_msg->size = size; in stm32f7_i2c_smbus_xfer()
1744 f7_msg->read_write = read_write; in stm32f7_i2c_smbus_xfer()
1745 f7_msg->smbus = true; in stm32f7_i2c_smbus_xfer()
1759 timeout = wait_for_completion_timeout(&i2c_dev->complete, in stm32f7_i2c_smbus_xfer()
1760 i2c_dev->adap.timeout); in stm32f7_i2c_smbus_xfer()
1761 ret = f7_msg->result; in stm32f7_i2c_smbus_xfer()
1763 if (i2c_dev->use_dma) in stm32f7_i2c_smbus_xfer()
1764 dmaengine_synchronize(dma->chan_using); in stm32f7_i2c_smbus_xfer()
1772 i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_smbus_xfer()
1777 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); in stm32f7_i2c_smbus_xfer()
1778 if (i2c_dev->use_dma) in stm32f7_i2c_smbus_xfer()
1779 dmaengine_terminate_sync(dma->chan_using); in stm32f7_i2c_smbus_xfer()
1781 ret = -ETIMEDOUT; in stm32f7_i2c_smbus_xfer()
1796 data->byte = f7_msg->smbus_buf[0]; in stm32f7_i2c_smbus_xfer()
1800 data->word = f7_msg->smbus_buf[0] | in stm32f7_i2c_smbus_xfer()
1801 (f7_msg->smbus_buf[1] << 8); in stm32f7_i2c_smbus_xfer()
1805 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) in stm32f7_i2c_smbus_xfer()
1806 data->block[i] = f7_msg->smbus_buf[i]; in stm32f7_i2c_smbus_xfer()
1810 ret = -EINVAL; in stm32f7_i2c_smbus_xfer()
1823 void __iomem *base = i2c_dev->base; in stm32f7_i2c_enable_wakeup()
1826 if (!i2c_dev->wakeup_src) in stm32f7_i2c_enable_wakeup()
1830 device_set_wakeup_enable(i2c_dev->dev, true); in stm32f7_i2c_enable_wakeup()
1833 device_set_wakeup_enable(i2c_dev->dev, false); in stm32f7_i2c_enable_wakeup()
1840 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); in stm32f7_i2c_reg_slave()
1841 void __iomem *base = i2c_dev->base; in stm32f7_i2c_reg_slave()
1842 struct device *dev = i2c_dev->dev; in stm32f7_i2c_reg_slave()
1846 if (slave->flags & I2C_CLIENT_PEC) { in stm32f7_i2c_reg_slave()
1848 return -EINVAL; in stm32f7_i2c_reg_slave()
1853 return -EBUSY; in stm32f7_i2c_reg_slave()
1870 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1875 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_reg_slave()
1877 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_reg_slave()
1878 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); in stm32f7_i2c_reg_slave()
1881 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); in stm32f7_i2c_reg_slave()
1884 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1885 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_reg_slave()
1890 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_reg_slave()
1892 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_reg_slave()
1893 ret = -EOPNOTSUPP; in stm32f7_i2c_reg_slave()
1897 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); in stm32f7_i2c_reg_slave()
1899 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1900 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_reg_slave()
1904 dev_err(dev, "I2C slave id not supported\n"); in stm32f7_i2c_reg_slave()
1905 ret = -ENODEV; in stm32f7_i2c_reg_slave()
1912 /* Enable Address match interrupt, error interrupt and enable I2C */ in stm32f7_i2c_reg_slave()
1930 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); in stm32f7_i2c_unreg_slave()
1931 void __iomem *base = i2c_dev->base; in stm32f7_i2c_unreg_slave()
1939 WARN_ON(!i2c_dev->slave[id]); in stm32f7_i2c_unreg_slave()
1941 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_unreg_slave()
1953 i2c_dev->slave[id] = NULL; in stm32f7_i2c_unreg_slave()
1960 pm_runtime_mark_last_busy(i2c_dev->dev); in stm32f7_i2c_unreg_slave()
1961 pm_runtime_put_autosuspend(i2c_dev->dev); in stm32f7_i2c_unreg_slave()
1971 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || in stm32f7_i2c_write_fm_plus_bits()
1972 IS_ERR_OR_NULL(i2c_dev->regmap)) in stm32f7_i2c_write_fm_plus_bits()
1976 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) in stm32f7_i2c_write_fm_plus_bits()
1977 ret = regmap_update_bits(i2c_dev->regmap, in stm32f7_i2c_write_fm_plus_bits()
1978 i2c_dev->fmp_sreg, in stm32f7_i2c_write_fm_plus_bits()
1979 i2c_dev->fmp_mask, in stm32f7_i2c_write_fm_plus_bits()
1980 enable ? i2c_dev->fmp_mask : 0); in stm32f7_i2c_write_fm_plus_bits()
1982 ret = regmap_write(i2c_dev->regmap, in stm32f7_i2c_write_fm_plus_bits()
1983 enable ? i2c_dev->fmp_sreg : in stm32f7_i2c_write_fm_plus_bits()
1984 i2c_dev->fmp_creg, in stm32f7_i2c_write_fm_plus_bits()
1985 i2c_dev->fmp_mask); in stm32f7_i2c_write_fm_plus_bits()
1993 struct device_node *np = pdev->dev.of_node; in stm32f7_i2c_setup_fm_plus_bits()
1996 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); in stm32f7_i2c_setup_fm_plus_bits()
1997 if (IS_ERR(i2c_dev->regmap)) in stm32f7_i2c_setup_fm_plus_bits()
2001 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, in stm32f7_i2c_setup_fm_plus_bits()
2002 &i2c_dev->fmp_sreg); in stm32f7_i2c_setup_fm_plus_bits()
2006 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + in stm32f7_i2c_setup_fm_plus_bits()
2007 i2c_dev->setup.fmp_clr_offset; in stm32f7_i2c_setup_fm_plus_bits()
2009 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, in stm32f7_i2c_setup_fm_plus_bits()
2010 &i2c_dev->fmp_mask); in stm32f7_i2c_setup_fm_plus_bits()
2015 struct i2c_adapter *adap = &i2c_dev->adap; in stm32f7_i2c_enable_smbus_host()
2016 void __iomem *base = i2c_dev->base; in stm32f7_i2c_enable_smbus_host()
2023 i2c_dev->host_notify_client = client; in stm32f7_i2c_enable_smbus_host()
2033 void __iomem *base = i2c_dev->base; in stm32f7_i2c_disable_smbus_host()
2035 if (i2c_dev->host_notify_client) { in stm32f7_i2c_disable_smbus_host()
2039 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client); in stm32f7_i2c_disable_smbus_host()
2046 struct i2c_adapter *adap = &i2c_dev->adap; in stm32f7_i2c_enable_smbus_alert()
2047 struct device *dev = i2c_dev->dev; in stm32f7_i2c_enable_smbus_alert()
2048 void __iomem *base = i2c_dev->base; in stm32f7_i2c_enable_smbus_alert()
2052 return -ENOMEM; in stm32f7_i2c_enable_smbus_alert()
2054 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); in stm32f7_i2c_enable_smbus_alert()
2055 if (IS_ERR(alert->ara)) in stm32f7_i2c_enable_smbus_alert()
2056 return PTR_ERR(alert->ara); in stm32f7_i2c_enable_smbus_alert()
2058 i2c_dev->alert = alert; in stm32f7_i2c_enable_smbus_alert()
2068 struct stm32f7_i2c_alert *alert = i2c_dev->alert; in stm32f7_i2c_disable_smbus_alert()
2069 void __iomem *base = i2c_dev->base; in stm32f7_i2c_disable_smbus_alert()
2075 i2c_unregister_device(alert->ara); in stm32f7_i2c_disable_smbus_alert()
2090 if (i2c_dev->smbus_mode) in stm32f7_i2c_func()
2114 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in stm32f7_i2c_probe()
2116 return -ENOMEM; in stm32f7_i2c_probe()
2118 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32f7_i2c_probe()
2119 if (IS_ERR(i2c_dev->base)) in stm32f7_i2c_probe()
2120 return PTR_ERR(i2c_dev->base); in stm32f7_i2c_probe()
2121 phy_addr = (dma_addr_t)res->start; in stm32f7_i2c_probe()
2125 return irq_event ? : -ENOENT; in stm32f7_i2c_probe()
2129 return irq_error ? : -ENOENT; in stm32f7_i2c_probe()
2131 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, in stm32f7_i2c_probe()
2132 "wakeup-source"); in stm32f7_i2c_probe()
2134 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); in stm32f7_i2c_probe()
2135 if (IS_ERR(i2c_dev->clk)) in stm32f7_i2c_probe()
2136 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), in stm32f7_i2c_probe()
2139 ret = clk_prepare_enable(i2c_dev->clk); in stm32f7_i2c_probe()
2141 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); in stm32f7_i2c_probe()
2145 rst = devm_reset_control_get(&pdev->dev, NULL); in stm32f7_i2c_probe()
2147 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), in stm32f7_i2c_probe()
2155 i2c_dev->dev = &pdev->dev; in stm32f7_i2c_probe()
2157 ret = devm_request_threaded_irq(&pdev->dev, irq_event, in stm32f7_i2c_probe()
2161 pdev->name, i2c_dev); in stm32f7_i2c_probe()
2163 dev_err(&pdev->dev, "Failed to request irq event %i\n", in stm32f7_i2c_probe()
2168 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, in stm32f7_i2c_probe()
2169 pdev->name, i2c_dev); in stm32f7_i2c_probe()
2171 dev_err(&pdev->dev, "Failed to request irq error %i\n", in stm32f7_i2c_probe()
2176 setup = of_device_get_match_data(&pdev->dev); in stm32f7_i2c_probe()
2178 dev_err(&pdev->dev, "Can't get device data\n"); in stm32f7_i2c_probe()
2179 ret = -ENODEV; in stm32f7_i2c_probe()
2182 i2c_dev->setup = *setup; in stm32f7_i2c_probe()
2184 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); in stm32f7_i2c_probe()
2189 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { in stm32f7_i2c_probe()
2198 adap = &i2c_dev->adap; in stm32f7_i2c_probe()
2200 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", in stm32f7_i2c_probe()
2201 &res->start); in stm32f7_i2c_probe()
2202 adap->owner = THIS_MODULE; in stm32f7_i2c_probe()
2203 adap->timeout = 2 * HZ; in stm32f7_i2c_probe()
2204 adap->retries = 3; in stm32f7_i2c_probe()
2205 adap->algo = &stm32f7_i2c_algo; in stm32f7_i2c_probe()
2206 adap->dev.parent = &pdev->dev; in stm32f7_i2c_probe()
2207 adap->dev.of_node = pdev->dev.of_node; in stm32f7_i2c_probe()
2209 init_completion(&i2c_dev->complete); in stm32f7_i2c_probe()
2212 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, in stm32f7_i2c_probe()
2215 if (IS_ERR(i2c_dev->dma)) { in stm32f7_i2c_probe()
2216 ret = PTR_ERR(i2c_dev->dma); in stm32f7_i2c_probe()
2218 if (ret != -ENODEV) in stm32f7_i2c_probe()
2220 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n"); in stm32f7_i2c_probe()
2221 i2c_dev->dma = NULL; in stm32f7_i2c_probe()
2224 if (i2c_dev->wakeup_src) { in stm32f7_i2c_probe()
2225 device_set_wakeup_capable(i2c_dev->dev, true); in stm32f7_i2c_probe()
2227 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); in stm32f7_i2c_probe()
2229 dev_err(i2c_dev->dev, "Failed to set wake up irq\n"); in stm32f7_i2c_probe()
2236 pm_runtime_set_autosuspend_delay(i2c_dev->dev, in stm32f7_i2c_probe()
2238 pm_runtime_use_autosuspend(i2c_dev->dev); in stm32f7_i2c_probe()
2239 pm_runtime_set_active(i2c_dev->dev); in stm32f7_i2c_probe()
2240 pm_runtime_enable(i2c_dev->dev); in stm32f7_i2c_probe()
2242 pm_runtime_get_noresume(&pdev->dev); in stm32f7_i2c_probe()
2246 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus"); in stm32f7_i2c_probe()
2252 if (i2c_dev->smbus_mode) { in stm32f7_i2c_probe()
2255 dev_err(i2c_dev->dev, in stm32f7_i2c_probe()
2256 "failed to enable SMBus Host-Notify protocol (%d)\n", in stm32f7_i2c_probe()
2262 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { in stm32f7_i2c_probe()
2265 dev_err(i2c_dev->dev, in stm32f7_i2c_probe()
2272 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); in stm32f7_i2c_probe()
2274 pm_runtime_mark_last_busy(i2c_dev->dev); in stm32f7_i2c_probe()
2275 pm_runtime_put_autosuspend(i2c_dev->dev); in stm32f7_i2c_probe()
2286 pm_runtime_put_noidle(i2c_dev->dev); in stm32f7_i2c_probe()
2287 pm_runtime_disable(i2c_dev->dev); in stm32f7_i2c_probe()
2288 pm_runtime_set_suspended(i2c_dev->dev); in stm32f7_i2c_probe()
2289 pm_runtime_dont_use_autosuspend(i2c_dev->dev); in stm32f7_i2c_probe()
2291 if (i2c_dev->wakeup_src) in stm32f7_i2c_probe()
2292 dev_pm_clear_wake_irq(i2c_dev->dev); in stm32f7_i2c_probe()
2295 if (i2c_dev->wakeup_src) in stm32f7_i2c_probe()
2296 device_set_wakeup_capable(i2c_dev->dev, false); in stm32f7_i2c_probe()
2298 if (i2c_dev->dma) { in stm32f7_i2c_probe()
2299 stm32_i2c_dma_free(i2c_dev->dma); in stm32f7_i2c_probe()
2300 i2c_dev->dma = NULL; in stm32f7_i2c_probe()
2307 clk_disable_unprepare(i2c_dev->clk); in stm32f7_i2c_probe()
2319 i2c_del_adapter(&i2c_dev->adap); in stm32f7_i2c_remove()
2320 pm_runtime_get_sync(i2c_dev->dev); in stm32f7_i2c_remove()
2322 if (i2c_dev->wakeup_src) { in stm32f7_i2c_remove()
2323 dev_pm_clear_wake_irq(i2c_dev->dev); in stm32f7_i2c_remove()
2328 device_init_wakeup(i2c_dev->dev, false); in stm32f7_i2c_remove()
2331 pm_runtime_put_noidle(i2c_dev->dev); in stm32f7_i2c_remove()
2332 pm_runtime_disable(i2c_dev->dev); in stm32f7_i2c_remove()
2333 pm_runtime_set_suspended(i2c_dev->dev); in stm32f7_i2c_remove()
2334 pm_runtime_dont_use_autosuspend(i2c_dev->dev); in stm32f7_i2c_remove()
2336 if (i2c_dev->dma) { in stm32f7_i2c_remove()
2337 stm32_i2c_dma_free(i2c_dev->dma); in stm32f7_i2c_remove()
2338 i2c_dev->dma = NULL; in stm32f7_i2c_remove()
2343 clk_disable_unprepare(i2c_dev->clk); in stm32f7_i2c_remove()
2353 clk_disable_unprepare(i2c_dev->clk); in stm32f7_i2c_runtime_suspend()
2364 ret = clk_prepare_enable(i2c_dev->clk); in stm32f7_i2c_runtime_resume()
2377 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; in stm32f7_i2c_regs_backup()
2379 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_regs_backup()
2383 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); in stm32f7_i2c_regs_backup()
2384 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_regs_backup()
2385 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_regs_backup()
2386 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_regs_backup()
2387 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); in stm32f7_i2c_regs_backup()
2390 pm_runtime_put_sync(i2c_dev->dev); in stm32f7_i2c_regs_backup()
2399 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; in stm32f7_i2c_regs_restore()
2401 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_regs_restore()
2405 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); in stm32f7_i2c_regs_restore()
2407 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_regs_restore()
2410 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); in stm32f7_i2c_regs_restore()
2411 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, in stm32f7_i2c_regs_restore()
2412 i2c_dev->base + STM32F7_I2C_CR1); in stm32f7_i2c_regs_restore()
2413 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) in stm32f7_i2c_regs_restore()
2414 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_regs_restore()
2416 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_regs_restore()
2417 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_regs_restore()
2418 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_regs_restore()
2421 pm_runtime_put_sync(i2c_dev->dev); in stm32f7_i2c_regs_restore()
2431 i2c_mark_adapter_suspended(&i2c_dev->adap); in stm32f7_i2c_suspend()
2436 i2c_mark_adapter_resumed(&i2c_dev->adap); in stm32f7_i2c_suspend()
2463 i2c_mark_adapter_resumed(&i2c_dev->adap); in stm32f7_i2c_resume()
2475 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2476 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2477 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup},
2484 .name = "stm32f7-i2c",
2495 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");