Lines Matching +full:parent +full:- +full:interrupt +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
13 * This driver is based on i2c-st.c
21 #include <linux/interrupt.h>
31 #include "i2c-stm32.h"
97 * struct stm32f4_i2c_msg - client specific data
98 * @addr: 8-bit slave addr, including r/w bit
113 * struct stm32f4_i2c_dev - private data of the controller
116 * @base: virtual memory area
120 * @parent_rate: I2C clock parent rate in MHz
126 void __iomem *base; member
146 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; in stm32f4_i2c_disable_irq()
156 i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk); in stm32f4_i2c_set_periph_clk_freq()
157 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); in stm32f4_i2c_set_periph_clk_freq()
159 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) { in stm32f4_i2c_set_periph_clk_freq()
161 * To reach 100 kHz, the parent clk frequency should be between in stm32f4_i2c_set_periph_clk_freq()
167 dev_err(i2c_dev->dev, in stm32f4_i2c_set_periph_clk_freq()
168 "bad parent clk freq for standard mode\n"); in stm32f4_i2c_set_periph_clk_freq()
169 return -EINVAL; in stm32f4_i2c_set_periph_clk_freq()
173 * To be as close as possible to 400 kHz, the parent clk in stm32f4_i2c_set_periph_clk_freq()
179 dev_err(i2c_dev->dev, in stm32f4_i2c_set_periph_clk_freq()
180 "bad parent clk freq for fast mode\n"); in stm32f4_i2c_set_periph_clk_freq()
181 return -EINVAL; in stm32f4_i2c_set_periph_clk_freq()
186 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); in stm32f4_i2c_set_periph_clk_freq()
193 u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); in stm32f4_i2c_set_rise_time()
212 * Function stm32f4_i2c_set_periph_clk_freq made sure that parent rate in stm32f4_i2c_set_rise_time()
216 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) in stm32f4_i2c_set_rise_time()
222 i2c_dev->base + STM32F4_I2C_TRISE); in stm32f4_i2c_set_rise_time()
230 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) { in stm32f4_i2c_set_speed_mode()
233 * t_scl_high = t_scl_low = CCR * I2C parent clk period in stm32f4_i2c_set_speed_mode()
235 * CCR = I2C parent rate / (100 kHz * 2) in stm32f4_i2c_set_speed_mode()
237 * For example with parent rate = 2 MHz: in stm32f4_i2c_set_speed_mode()
243 * parent rate is not higher than 46 MHz . As a result val in stm32f4_i2c_set_speed_mode()
246 val = i2c_dev->parent_rate / (I2C_MAX_STANDARD_MODE_FREQ * 2); in stm32f4_i2c_set_speed_mode()
252 * t_scl_high = CCR * I2C parent clk period in stm32f4_i2c_set_speed_mode()
253 * t_scl_low = 2 * CCR * I2C parent clk period in stm32f4_i2c_set_speed_mode()
254 * So, CCR = I2C parent rate / (400 kHz * 3) in stm32f4_i2c_set_speed_mode()
256 * For example with parent rate = 6 MHz: in stm32f4_i2c_set_speed_mode()
263 * parent rate is not higher than 46 MHz . As a result val in stm32f4_i2c_set_speed_mode()
266 val = DIV_ROUND_UP(i2c_dev->parent_rate, I2C_MAX_FAST_MODE_FREQ * 3); in stm32f4_i2c_set_speed_mode()
273 writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR); in stm32f4_i2c_set_speed_mode()
277 * stm32f4_i2c_hw_config() - Prepare I2C block
293 writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_hw_config()
303 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2, in stm32f4_i2c_wait_free_bus()
308 dev_dbg(i2c_dev->dev, "bus not free\n"); in stm32f4_i2c_wait_free_bus()
309 ret = -EBUSY; in stm32f4_i2c_wait_free_bus()
316 * stm32f4_i2c_write_byte() - Write a byte in the data register
322 writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR); in stm32f4_i2c_write_byte()
326 * stm32f4_i2c_write_msg() - Fill the data register in write mode
333 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; in stm32f4_i2c_write_msg()
335 stm32f4_i2c_write_byte(i2c_dev, *msg->buf++); in stm32f4_i2c_write_msg()
336 msg->count--; in stm32f4_i2c_write_msg()
341 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; in stm32f4_i2c_read_msg()
344 rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR); in stm32f4_i2c_read_msg()
345 *msg->buf++ = rbuf; in stm32f4_i2c_read_msg()
346 msg->count--; in stm32f4_i2c_read_msg()
351 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; in stm32f4_i2c_terminate_xfer()
356 reg = i2c_dev->base + STM32F4_I2C_CR1; in stm32f4_i2c_terminate_xfer()
357 if (msg->stop) in stm32f4_i2c_terminate_xfer()
362 complete(&i2c_dev->complete); in stm32f4_i2c_terminate_xfer()
366 * stm32f4_i2c_handle_write() - Handle FIFO empty interrupt in case of write
371 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; in stm32f4_i2c_handle_write()
372 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; in stm32f4_i2c_handle_write()
374 if (msg->count) { in stm32f4_i2c_handle_write()
376 if (!msg->count) { in stm32f4_i2c_handle_write()
389 * stm32f4_i2c_handle_read() - Handle FIFO empty interrupt in case of read
396 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; in stm32f4_i2c_handle_read()
397 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; in stm32f4_i2c_handle_read()
399 switch (msg->count) { in stm32f4_i2c_handle_read()
403 complete(&i2c_dev->complete); in stm32f4_i2c_handle_read()
406 * For 2-byte reception, 3-byte reception and for Data N-2, N-1 and N in stm32f4_i2c_handle_read()
407 * for N-byte reception with N > 3, we do not have to read the data in stm32f4_i2c_handle_read()
410 * So, here we just disable buffer interrupt in order to avoid another in stm32f4_i2c_handle_read()
419 * until N-2 data. in stm32f4_i2c_handle_read()
427 * stm32f4_i2c_handle_rx_done() - Handle byte transfer finished interrupt
436 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; in stm32f4_i2c_handle_rx_done()
441 switch (msg->count) { in stm32f4_i2c_handle_rx_done()
446 * before reading the last two bytes (data N-1 and N). in stm32f4_i2c_handle_rx_done()
451 reg = i2c_dev->base + STM32F4_I2C_CR1; in stm32f4_i2c_handle_rx_done()
452 if (msg->stop) in stm32f4_i2c_handle_rx_done()
457 for (i = 2; i > 0; i--) in stm32f4_i2c_handle_rx_done()
460 reg = i2c_dev->base + STM32F4_I2C_CR2; in stm32f4_i2c_handle_rx_done()
464 complete(&i2c_dev->complete); in stm32f4_i2c_handle_rx_done()
469 * received data byte, we have to enable NACK before reading N-2 in stm32f4_i2c_handle_rx_done()
472 reg = i2c_dev->base + STM32F4_I2C_CR1; in stm32f4_i2c_handle_rx_done()
482 * stm32f4_i2c_handle_rx_addr() - Handle address matched interrupt in case of
488 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; in stm32f4_i2c_handle_rx_addr()
491 switch (msg->count) { in stm32f4_i2c_handle_rx_addr()
496 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); in stm32f4_i2c_handle_rx_addr()
506 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
508 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
510 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); in stm32f4_i2c_handle_rx_addr()
512 if (msg->stop) in stm32f4_i2c_handle_rx_addr()
516 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
520 * 2-byte reception: in stm32f4_i2c_handle_rx_addr()
526 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
529 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
531 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); in stm32f4_i2c_handle_rx_addr()
536 * N-byte reception: in stm32f4_i2c_handle_rx_addr()
541 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
544 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
546 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); in stm32f4_i2c_handle_rx_addr()
552 * stm32f4_i2c_isr_event() - Interrupt routine for I2C bus event
553 * @irq: interrupt number
559 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; in stm32f4_i2c_isr_event()
563 cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2); in stm32f4_i2c_isr_event()
566 /* Update possible_status if buffer interrupt is enabled */ in stm32f4_i2c_isr_event()
570 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); in stm32f4_i2c_isr_event()
573 dev_dbg(i2c_dev->dev, in stm32f4_i2c_isr_event()
581 stm32f4_i2c_write_byte(i2c_dev, msg->addr); in stm32f4_i2c_isr_event()
585 if (msg->addr & I2C_M_RD) in stm32f4_i2c_isr_event()
588 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); in stm32f4_i2c_isr_event()
595 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); in stm32f4_i2c_isr_event()
599 if ((event & STM32F4_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD)) in stm32f4_i2c_isr_event()
603 if ((event & STM32F4_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD)) in stm32f4_i2c_isr_event()
608 * - in reception : a new byte is received in the shift register in stm32f4_i2c_isr_event()
610 * - in transmission: a new byte should be sent but the data register in stm32f4_i2c_isr_event()
614 if (msg->addr & I2C_M_RD) in stm32f4_i2c_isr_event()
624 * stm32f4_i2c_isr_error() - Interrupt routine for I2C bus error
625 * @irq: interrupt number
631 struct stm32f4_i2c_msg *msg = &i2c_dev->msg; in stm32f4_i2c_isr_error()
635 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); in stm32f4_i2c_isr_error()
640 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); in stm32f4_i2c_isr_error()
641 msg->result = -EAGAIN; in stm32f4_i2c_isr_error()
649 if (!(msg->addr & I2C_M_RD)) { in stm32f4_i2c_isr_error()
650 reg = i2c_dev->base + STM32F4_I2C_CR1; in stm32f4_i2c_isr_error()
654 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); in stm32f4_i2c_isr_error()
655 msg->result = -EIO; in stm32f4_i2c_isr_error()
661 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); in stm32f4_i2c_isr_error()
662 msg->result = -EIO; in stm32f4_i2c_isr_error()
666 complete(&i2c_dev->complete); in stm32f4_i2c_isr_error()
672 * stm32f4_i2c_xfer_msg() - Transfer a single I2C message
682 struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg; in stm32f4_i2c_xfer_msg()
683 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1; in stm32f4_i2c_xfer_msg()
688 f4_msg->addr = i2c_8bit_addr_from_msg(msg); in stm32f4_i2c_xfer_msg()
689 f4_msg->buf = msg->buf; in stm32f4_i2c_xfer_msg()
690 f4_msg->count = msg->len; in stm32f4_i2c_xfer_msg()
691 f4_msg->result = 0; in stm32f4_i2c_xfer_msg()
692 f4_msg->stop = is_last; in stm32f4_i2c_xfer_msg()
694 reinit_completion(&i2c_dev->complete); in stm32f4_i2c_xfer_msg()
698 stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask); in stm32f4_i2c_xfer_msg()
709 timeout = wait_for_completion_timeout(&i2c_dev->complete, in stm32f4_i2c_xfer_msg()
710 i2c_dev->adap.timeout); in stm32f4_i2c_xfer_msg()
711 ret = f4_msg->result; in stm32f4_i2c_xfer_msg()
714 ret = -ETIMEDOUT; in stm32f4_i2c_xfer_msg()
720 * stm32f4_i2c_xfer() - Transfer combined I2C message
731 ret = clk_enable(i2c_dev->clk); in stm32f4_i2c_xfer()
733 dev_err(i2c_dev->dev, "Failed to enable clock\n"); in stm32f4_i2c_xfer()
739 i == num - 1); in stm32f4_i2c_xfer()
741 clk_disable(i2c_dev->clk); in stm32f4_i2c_xfer()
758 struct device_node *np = pdev->dev.of_node; in stm32f4_i2c_probe()
766 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in stm32f4_i2c_probe()
768 return -ENOMEM; in stm32f4_i2c_probe()
771 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); in stm32f4_i2c_probe()
772 if (IS_ERR(i2c_dev->base)) in stm32f4_i2c_probe()
773 return PTR_ERR(i2c_dev->base); in stm32f4_i2c_probe()
777 dev_err(&pdev->dev, "IRQ event missing or invalid\n"); in stm32f4_i2c_probe()
778 return -EINVAL; in stm32f4_i2c_probe()
783 dev_err(&pdev->dev, "IRQ error missing or invalid\n"); in stm32f4_i2c_probe()
784 return -EINVAL; in stm32f4_i2c_probe()
787 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); in stm32f4_i2c_probe()
788 if (IS_ERR(i2c_dev->clk)) { in stm32f4_i2c_probe()
789 dev_err(&pdev->dev, "Error: Missing controller clock\n"); in stm32f4_i2c_probe()
790 return PTR_ERR(i2c_dev->clk); in stm32f4_i2c_probe()
792 ret = clk_prepare_enable(i2c_dev->clk); in stm32f4_i2c_probe()
794 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n"); in stm32f4_i2c_probe()
798 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in stm32f4_i2c_probe()
800 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), in stm32f4_i2c_probe()
808 i2c_dev->speed = STM32_I2C_SPEED_STANDARD; in stm32f4_i2c_probe()
809 ret = of_property_read_u32(np, "clock-frequency", &clk_rate); in stm32f4_i2c_probe()
811 i2c_dev->speed = STM32_I2C_SPEED_FAST; in stm32f4_i2c_probe()
813 i2c_dev->dev = &pdev->dev; in stm32f4_i2c_probe()
815 ret = devm_request_irq(&pdev->dev, irq_event, stm32f4_i2c_isr_event, 0, in stm32f4_i2c_probe()
816 pdev->name, i2c_dev); in stm32f4_i2c_probe()
818 dev_err(&pdev->dev, "Failed to request irq event %i\n", in stm32f4_i2c_probe()
823 ret = devm_request_irq(&pdev->dev, irq_error, stm32f4_i2c_isr_error, 0, in stm32f4_i2c_probe()
824 pdev->name, i2c_dev); in stm32f4_i2c_probe()
826 dev_err(&pdev->dev, "Failed to request irq error %i\n", in stm32f4_i2c_probe()
835 adap = &i2c_dev->adap; in stm32f4_i2c_probe()
837 snprintf(adap->name, sizeof(adap->name), "STM32 I2C(%pa)", &res->start); in stm32f4_i2c_probe()
838 adap->owner = THIS_MODULE; in stm32f4_i2c_probe()
839 adap->timeout = 2 * HZ; in stm32f4_i2c_probe()
840 adap->retries = 0; in stm32f4_i2c_probe()
841 adap->algo = &stm32f4_i2c_algo; in stm32f4_i2c_probe()
842 adap->dev.parent = &pdev->dev; in stm32f4_i2c_probe()
843 adap->dev.of_node = pdev->dev.of_node; in stm32f4_i2c_probe()
845 init_completion(&i2c_dev->complete); in stm32f4_i2c_probe()
853 clk_disable(i2c_dev->clk); in stm32f4_i2c_probe()
855 dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n"); in stm32f4_i2c_probe()
860 clk_disable_unprepare(i2c_dev->clk); in stm32f4_i2c_probe()
868 i2c_del_adapter(&i2c_dev->adap); in stm32f4_i2c_remove()
870 clk_unprepare(i2c_dev->clk); in stm32f4_i2c_remove()
876 { .compatible = "st,stm32f4-i2c", },
883 .name = "stm32f4-i2c",