141 #define NPCM_I2CFIF_CTS			0x10 /* Both FIFOs Control and Status */  macro
486 	val = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_clear_fifo_int()
488 	iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_clear_fifo_int()
674 	iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_reset()
1071 				 bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1096 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1143 				 bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1151 				       ioread8(bus->reg + NPCM_I2CFIF_CTS))) {  in npcm_i2c_int_slave_handler()
1160 		iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1437 				data = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_master_handler_read()
1439 				iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_master_handler_read()
1488 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_nack()
1607 		fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1612 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1616 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1729 	fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_recovery_tgclk()
1732 	iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_recovery_tgclk()
2075 		i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_master_start_xmit()
2078 		iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_master_start_xmit()