1 // SPDX-License-Identifier: GPL-2.0+
5  * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
6  * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
8  * based on a (non-working) driver which was:
10  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
26 #include <linux/dma-mapping.h>
28 #include <linux/dma/mxs-dma.h>
30 #define DRIVER_NAME "mxs-i2c"
70 #define MXS_I2C_DATA(i2c)	((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
72 #define MXS_I2C_DEBUG0_CLR(i2c)	((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
104  * struct mxs_i2c_dev - per device, private MXS-I2C data
135 	int ret = stmp_reset_block(i2c->regs);  in mxs_i2c_reset()
144 	 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].  in mxs_i2c_reset()
146 	writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);  in mxs_i2c_reset()
147 	writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);  in mxs_i2c_reset()
148 	writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);  in mxs_i2c_reset()
150 	writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);  in mxs_i2c_reset()
157 	if (i2c->dma_read) {  in mxs_i2c_dma_finish()
158 		dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);  in mxs_i2c_dma_finish()
159 		dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);  in mxs_i2c_dma_finish()
161 		dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);  in mxs_i2c_dma_finish()
169 	complete(&i2c->cmd_complete);  in mxs_i2c_dma_irq_callback()
179 	i2c->addr_data = i2c_8bit_addr_from_msg(msg);  in mxs_i2c_dma_setup_xfer()
181 	if (msg->flags & I2C_M_RD) {  in mxs_i2c_dma_setup_xfer()
182 		i2c->dma_read = true;  in mxs_i2c_dma_setup_xfer()
188 		/* Queue the PIO register write transfer. */  in mxs_i2c_dma_setup_xfer()
189 		i2c->pio_data[0] = MXS_CMD_I2C_SELECT;  in mxs_i2c_dma_setup_xfer()
190 		desc = dmaengine_prep_slave_sg(i2c->dmach,  in mxs_i2c_dma_setup_xfer()
191 					(struct scatterlist *)&i2c->pio_data[0],  in mxs_i2c_dma_setup_xfer()
194 			dev_err(i2c->dev,  in mxs_i2c_dma_setup_xfer()
195 				"Failed to get PIO reg. write descriptor.\n");  in mxs_i2c_dma_setup_xfer()
199 		/* Queue the DMA data transfer. */  in mxs_i2c_dma_setup_xfer()
200 		sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);  in mxs_i2c_dma_setup_xfer()
201 		dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);  in mxs_i2c_dma_setup_xfer()
202 		desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,  in mxs_i2c_dma_setup_xfer()
207 			dev_err(i2c->dev,  in mxs_i2c_dma_setup_xfer()
216 		/* Queue the PIO register write transfer. */  in mxs_i2c_dma_setup_xfer()
217 		i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |  in mxs_i2c_dma_setup_xfer()
218 				MXS_I2C_CTRL0_XFER_COUNT(msg->len);  in mxs_i2c_dma_setup_xfer()
219 		desc = dmaengine_prep_slave_sg(i2c->dmach,  in mxs_i2c_dma_setup_xfer()
220 					(struct scatterlist *)&i2c->pio_data[1],  in mxs_i2c_dma_setup_xfer()
223 			dev_err(i2c->dev,  in mxs_i2c_dma_setup_xfer()
224 				"Failed to get PIO reg. write descriptor.\n");  in mxs_i2c_dma_setup_xfer()
228 		/* Queue the DMA data transfer. */  in mxs_i2c_dma_setup_xfer()
229 		sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);  in mxs_i2c_dma_setup_xfer()
230 		dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);  in mxs_i2c_dma_setup_xfer()
231 		desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,  in mxs_i2c_dma_setup_xfer()
236 			dev_err(i2c->dev,  in mxs_i2c_dma_setup_xfer()
241 		i2c->dma_read = false;  in mxs_i2c_dma_setup_xfer()
247 		/* Queue the PIO register write transfer. */  in mxs_i2c_dma_setup_xfer()
248 		i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |  in mxs_i2c_dma_setup_xfer()
249 				MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);  in mxs_i2c_dma_setup_xfer()
250 		desc = dmaengine_prep_slave_sg(i2c->dmach,  in mxs_i2c_dma_setup_xfer()
251 					(struct scatterlist *)&i2c->pio_data[0],  in mxs_i2c_dma_setup_xfer()
254 			dev_err(i2c->dev,  in mxs_i2c_dma_setup_xfer()
255 				"Failed to get PIO reg. write descriptor.\n");  in mxs_i2c_dma_setup_xfer()
259 		/* Queue the DMA data transfer. */  in mxs_i2c_dma_setup_xfer()
260 		sg_init_table(i2c->sg_io, 2);  in mxs_i2c_dma_setup_xfer()
261 		sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);  in mxs_i2c_dma_setup_xfer()
262 		sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);  in mxs_i2c_dma_setup_xfer()
263 		dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);  in mxs_i2c_dma_setup_xfer()
264 		desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,  in mxs_i2c_dma_setup_xfer()
269 			dev_err(i2c->dev,  in mxs_i2c_dma_setup_xfer()
279 	desc->callback = mxs_i2c_dma_irq_callback;  in mxs_i2c_dma_setup_xfer()
280 	desc->callback_param = i2c;  in mxs_i2c_dma_setup_xfer()
282 	/* Start the transfer. */  in mxs_i2c_dma_setup_xfer()
284 	dma_async_issue_pending(i2c->dmach);  in mxs_i2c_dma_setup_xfer()
289 	dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);  in mxs_i2c_dma_setup_xfer()
291 	dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);  in mxs_i2c_dma_setup_xfer()
293 	dmaengine_terminate_sync(i2c->dmach);  in mxs_i2c_dma_setup_xfer()
294 	return -EINVAL;  in mxs_i2c_dma_setup_xfer()
298 	dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);  in mxs_i2c_dma_setup_xfer()
300 	dmaengine_terminate_sync(i2c->dmach);  in mxs_i2c_dma_setup_xfer()
301 	return -EINVAL;  in mxs_i2c_dma_setup_xfer()
308 	while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {  in mxs_i2c_pio_wait_xfer_end()
309 		if (readl(i2c->regs + MXS_I2C_CTRL1) &  in mxs_i2c_pio_wait_xfer_end()
311 			return -ENXIO;  in mxs_i2c_pio_wait_xfer_end()
313 			return -ETIMEDOUT;  in mxs_i2c_pio_wait_xfer_end()
324 	state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;  in mxs_i2c_pio_check_error_state()
327 		i2c->cmd_err = -ENXIO;  in mxs_i2c_pio_check_error_state()
332 		i2c->cmd_err = -EIO;  in mxs_i2c_pio_check_error_state()
334 	return i2c->cmd_err;  in mxs_i2c_pio_check_error_state()
341 	writel(cmd, i2c->regs + MXS_I2C_CTRL0);  in mxs_i2c_pio_trigger_cmd()
344 	reg = readl(i2c->regs + MXS_I2C_CTRL0);  in mxs_i2c_pio_trigger_cmd()
346 	writel(reg, i2c->regs + MXS_I2C_CTRL0);  in mxs_i2c_pio_trigger_cmd()
352  * must be written during PIO mode operation. First, the CTRL0 register has
360 	writel(cmd, i2c->regs + MXS_I2C_CTRL0);  in mxs_i2c_pio_trigger_write_cmd()
362 	if (i2c->dev_type == MXS_I2C_V1)  in mxs_i2c_pio_trigger_write_cmd()
363 		writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);  in mxs_i2c_pio_trigger_write_cmd()
365 	writel(data, i2c->regs + MXS_I2C_DATA(i2c));  in mxs_i2c_pio_trigger_write_cmd()
366 	writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);  in mxs_i2c_pio_trigger_write_cmd()
379 	writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);  in mxs_i2c_pio_setup_xfer()
383 	 * - Enable CTRL0::PIO_MODE (1 << 24)  in mxs_i2c_pio_setup_xfer()
384 	 * - Enable CTRL1::ACK_MODE (1 << 27)  in mxs_i2c_pio_setup_xfer()
387 	 * to support PIO, when we try to transfer any amount of data  in mxs_i2c_pio_setup_xfer()
390 	 * transfer. This in turn will mess up the next transfer as  in mxs_i2c_pio_setup_xfer()
393 	 * block after every PIO transmission, which might just work.  in mxs_i2c_pio_setup_xfer()
396 	 * it outlines how the PIO mode is really supposed to work.  in mxs_i2c_pio_setup_xfer()
398 	if (msg->flags & I2C_M_RD) {  in mxs_i2c_pio_setup_xfer()
400 		 * PIO READ transfer:  in mxs_i2c_pio_setup_xfer()
402 		 * This transfer MUST be limited to 4 bytes maximum. It is not  in mxs_i2c_pio_setup_xfer()
403 		 * possible to transfer more than four bytes via PIO, since we  in mxs_i2c_pio_setup_xfer()
411 		BUG_ON(msg->len > 4);  in mxs_i2c_pio_setup_xfer()
419 			dev_dbg(i2c->dev,  in mxs_i2c_pio_setup_xfer()
420 				"PIO: Failed to send SELECT command!\n");  in mxs_i2c_pio_setup_xfer()
427 					MXS_I2C_CTRL0_XFER_COUNT(msg->len));  in mxs_i2c_pio_setup_xfer()
431 			dev_dbg(i2c->dev,  in mxs_i2c_pio_setup_xfer()
432 				"PIO: Failed to send READ command!\n");  in mxs_i2c_pio_setup_xfer()
436 		data = readl(i2c->regs + MXS_I2C_DATA(i2c));  in mxs_i2c_pio_setup_xfer()
437 		for (i = 0; i < msg->len; i++) {  in mxs_i2c_pio_setup_xfer()
438 			msg->buf[i] = data & 0xff;  in mxs_i2c_pio_setup_xfer()
443 		 * PIO WRITE transfer:  in mxs_i2c_pio_setup_xfer()
447 		 * fast enough. It is possible to transfer arbitrary amount  in mxs_i2c_pio_setup_xfer()
448 		 * of data using PIO write.  in mxs_i2c_pio_setup_xfer()
459 		/* Start the transfer with START condition. */  in mxs_i2c_pio_setup_xfer()
462 		/* If the transfer is long, use clock stretching. */  in mxs_i2c_pio_setup_xfer()
463 		if (msg->len > 3)  in mxs_i2c_pio_setup_xfer()
466 		for (i = 0; i < msg->len; i++) {  in mxs_i2c_pio_setup_xfer()
468 			data |= (msg->buf[i] << 24);  in mxs_i2c_pio_setup_xfer()
472 			/* This is the last transfer of the message. */  in mxs_i2c_pio_setup_xfer()
473 			if (i + 1 == msg->len) {  in mxs_i2c_pio_setup_xfer()
490 			 * Compute the size of the transfer and shift the  in mxs_i2c_pio_setup_xfer()
504 			data >>= (4 - xlen) * 8;  in mxs_i2c_pio_setup_xfer()
506 			dev_dbg(i2c->dev,  in mxs_i2c_pio_setup_xfer()
507 				"PIO: len=%i pos=%i total=%i [W%s%s%s]\n",  in mxs_i2c_pio_setup_xfer()
508 				xlen, i, msg->len,  in mxs_i2c_pio_setup_xfer()
514 			       i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));  in mxs_i2c_pio_setup_xfer()
524 			/* Wait for the end of the transfer. */  in mxs_i2c_pio_setup_xfer()
527 				dev_dbg(i2c->dev,  in mxs_i2c_pio_setup_xfer()
528 					"PIO: Failed to finish WRITE cmd!\n");  in mxs_i2c_pio_setup_xfer()
533 			ret = readl(i2c->regs + MXS_I2C_STAT) &  in mxs_i2c_pio_setup_xfer()
536 				ret = -ENXIO;  in mxs_i2c_pio_setup_xfer()
546 	/* Clear any dangling IRQs and re-enable interrupts. */  in mxs_i2c_pio_setup_xfer()
547 	writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);  in mxs_i2c_pio_setup_xfer()
548 	writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);  in mxs_i2c_pio_setup_xfer()
551 	if (i2c->dev_type == MXS_I2C_V1)  in mxs_i2c_pio_setup_xfer()
552 		writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);  in mxs_i2c_pio_setup_xfer()
571 	dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",  in mxs_i2c_xfer_msg()
572 		msg->addr, msg->len, msg->flags, stop);  in mxs_i2c_xfer_msg()
575 	 * The MX28 I2C IP block can only do PIO READ for transfer of to up  in mxs_i2c_xfer_msg()
576 	 * 4 bytes of length. The write transfer is not limited as it can use  in mxs_i2c_xfer_msg()
579 	if ((msg->flags & I2C_M_RD) && (msg->len <= 4))  in mxs_i2c_xfer_msg()
581 	if (!(msg->flags & I2C_M_RD) && (msg->len < 7))  in mxs_i2c_xfer_msg()
584 	i2c->cmd_err = 0;  in mxs_i2c_xfer_msg()
588 		if (ret && (ret != -ENXIO))  in mxs_i2c_xfer_msg()
591 		reinit_completion(&i2c->cmd_complete);  in mxs_i2c_xfer_msg()
596 		time_left = wait_for_completion_timeout(&i2c->cmd_complete,  in mxs_i2c_xfer_msg()
601 		ret = i2c->cmd_err;  in mxs_i2c_xfer_msg()
604 	if (ret == -ENXIO) {  in mxs_i2c_xfer_msg()
606 		 * If the transfer fails with a NAK from the slave the  in mxs_i2c_xfer_msg()
610 		       i2c->regs + MXS_I2C_CTRL1_SET);  in mxs_i2c_xfer_msg()
622 	 * reset the block after every transfer to play safe.  in mxs_i2c_xfer_msg()
624 	if (i2c->dev_type == MXS_I2C_V1)  in mxs_i2c_xfer_msg()
627 	dev_dbg(i2c->dev, "Done with err=%d\n", ret);  in mxs_i2c_xfer_msg()
632 	dev_dbg(i2c->dev, "Timeout!\n");  in mxs_i2c_xfer_msg()
638 	return -ETIMEDOUT;  in mxs_i2c_xfer_msg()
648 		err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));  in mxs_i2c_xfer()
664 	u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;  in mxs_i2c_isr()
670 		i2c->cmd_err = -ENXIO;  in mxs_i2c_isr()
675 		i2c->cmd_err = -EIO;  in mxs_i2c_isr()
677 	writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);  in mxs_i2c_isr()
698 	struct device *dev = i2c->dev;  in mxs_i2c_derive_timing()
759 	low_count -= 2;  in mxs_i2c_derive_timing()
760 	high_count -= 7;  in mxs_i2c_derive_timing()
761 	i2c->timing0 = (high_count << 16) | rcv_count;  in mxs_i2c_derive_timing()
762 	i2c->timing1 = (low_count << 16) | xmit_count;  in mxs_i2c_derive_timing()
763 	i2c->timing2 = (bus_free << 16 | leadin);  in mxs_i2c_derive_timing()
769 	struct device *dev = i2c->dev;  in mxs_i2c_get_ofdata()
770 	struct device_node *node = dev->of_node;  in mxs_i2c_get_ofdata()
773 	ret = of_property_read_u32(node, "clock-frequency", &speed);  in mxs_i2c_get_ofdata()
785 	{ .compatible = "fsl,imx23-i2c", .data = (void *)MXS_I2C_V1, },
786 	{ .compatible = "fsl,imx28-i2c", .data = (void *)MXS_I2C_V2, },
793 	struct device *dev = &pdev->dev;  in mxs_i2c_probe()
800 		return -ENOMEM;  in mxs_i2c_probe()
802 	i2c->dev_type = (uintptr_t)of_device_get_match_data(&pdev->dev);  in mxs_i2c_probe()
804 	i2c->regs = devm_platform_ioremap_resource(pdev, 0);  in mxs_i2c_probe()
805 	if (IS_ERR(i2c->regs))  in mxs_i2c_probe()
806 		return PTR_ERR(i2c->regs);  in mxs_i2c_probe()
816 	i2c->dev = dev;  in mxs_i2c_probe()
818 	init_completion(&i2c->cmd_complete);  in mxs_i2c_probe()
820 	if (dev->of_node) {  in mxs_i2c_probe()
827 	i2c->dmach = dma_request_chan(dev, "rx-tx");  in mxs_i2c_probe()
828 	if (IS_ERR(i2c->dmach)) {  in mxs_i2c_probe()
830 		return PTR_ERR(i2c->dmach);  in mxs_i2c_probe()
840 	adap = &i2c->adapter;  in mxs_i2c_probe()
841 	strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name));  in mxs_i2c_probe()
842 	adap->owner = THIS_MODULE;  in mxs_i2c_probe()
843 	adap->algo = &mxs_i2c_algo;  in mxs_i2c_probe()
844 	adap->quirks = &mxs_i2c_quirks;  in mxs_i2c_probe()
845 	adap->dev.parent = dev;  in mxs_i2c_probe()
846 	adap->nr = pdev->id;  in mxs_i2c_probe()
847 	adap->dev.of_node = pdev->dev.of_node;  in mxs_i2c_probe()
852 				i2c->regs + MXS_I2C_CTRL0_SET);  in mxs_i2c_probe()
863 	i2c_del_adapter(&i2c->adapter);  in mxs_i2c_remove()
865 	if (i2c->dmach)  in mxs_i2c_remove()
866 		dma_release_channel(i2c->dmach);  in mxs_i2c_remove()
868 	writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);  in mxs_i2c_remove()