516 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)  in mtk_i2c_readw()  function
534 	intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);  in mtk_i2c_init_hw()
924 		mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),  in i2c_dump_register()
925 		mtk_i2c_readw(i2c, OFFSET_INTR_MASK));  in i2c_dump_register()
927 		mtk_i2c_readw(i2c, OFFSET_INTR_STAT),  in i2c_dump_register()
928 		mtk_i2c_readw(i2c, OFFSET_CONTROL));  in i2c_dump_register()
930 		mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),  in i2c_dump_register()
931 		mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));  in i2c_dump_register()
933 		mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),  in i2c_dump_register()
934 		mtk_i2c_readw(i2c, OFFSET_TIMING));  in i2c_dump_register()
936 		mtk_i2c_readw(i2c, OFFSET_START),  in i2c_dump_register()
937 		mtk_i2c_readw(i2c, OFFSET_EXT_CONF));  in i2c_dump_register()
939 		mtk_i2c_readw(i2c, OFFSET_HS),  in i2c_dump_register()
940 		mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));  in i2c_dump_register()
942 		mtk_i2c_readw(i2c, OFFSET_DCM_EN),  in i2c_dump_register()
943 		mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));  in i2c_dump_register()
945 		mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),  in i2c_dump_register()
946 		mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));  in i2c_dump_register()
948 		mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),  in i2c_dump_register()
949 		mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));  in i2c_dump_register()
952 			mtk_i2c_readw(i2c, OFFSET_LTIMING),  in i2c_dump_register()
953 			mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));  in i2c_dump_register()
1017 	control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &  in mtk_i2c_do_transfer()
1290 	intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);  in mtk_i2c_irq()