Lines Matching full:i2c
14 #include <linux/i2c.h>
87 #define I2C_DRV_NAME "i2c-mt65xx"
90 * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C
92 * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
93 * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA
94 * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
95 * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c
289 struct i2c_adapter adap; /* i2c host adapter */
294 /* set in i2c probe */
295 void __iomem *base; /* i2c base addr */
297 struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */
298 bool have_pmic; /* can use i2c pins from PMIC */
502 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
503 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
504 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
505 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
506 { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
507 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
508 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
509 { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
510 { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
511 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
516 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) in mtk_i2c_readw() argument
518 return readw(i2c->base + i2c->dev_comp->regs[reg]); in mtk_i2c_readw()
521 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, in mtk_i2c_writew() argument
524 writew(val, i2c->base + i2c->dev_comp->regs[reg]); in mtk_i2c_writew()
527 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) in mtk_i2c_init_hw() argument
533 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START); in mtk_i2c_init_hw()
534 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); in mtk_i2c_init_hw()
535 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT); in mtk_i2c_init_hw()
537 if (i2c->dev_comp->apdma_sync) { in mtk_i2c_init_hw()
538 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
540 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
543 i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
544 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, in mtk_i2c_init_hw()
547 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
548 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); in mtk_i2c_init_hw()
550 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
552 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
553 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); in mtk_i2c_init_hw()
557 if (i2c->use_push_pull) in mtk_i2c_init_hw()
558 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); in mtk_i2c_init_hw()
560 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); in mtk_i2c_init_hw()
562 if (i2c->dev_comp->dcm) in mtk_i2c_init_hw()
563 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); in mtk_i2c_init_hw()
565 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); in mtk_i2c_init_hw()
566 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); in mtk_i2c_init_hw()
567 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_init_hw()
568 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); in mtk_i2c_init_hw()
570 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) in mtk_i2c_init_hw()
575 if (i2c->dev_comp->timing_adjust) { in mtk_i2c_init_hw()
576 ext_conf_val = i2c->ac_timing.ext; in mtk_i2c_init_hw()
577 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, in mtk_i2c_init_hw()
579 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, in mtk_i2c_init_hw()
581 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, in mtk_i2c_init_hw()
584 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_init_hw()
585 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, in mtk_i2c_init_hw()
587 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); in mtk_i2c_init_hw()
588 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, in mtk_i2c_init_hw()
591 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, in mtk_i2c_init_hw()
593 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, in mtk_i2c_init_hw()
595 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, in mtk_i2c_init_hw()
597 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, in mtk_i2c_init_hw()
601 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF); in mtk_i2c_init_hw()
603 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ in mtk_i2c_init_hw()
604 if (i2c->have_pmic) in mtk_i2c_init_hw()
605 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); in mtk_i2c_init_hw()
609 if (i2c->dev_comp->dma_sync) in mtk_i2c_init_hw()
612 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_init_hw()
613 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); in mtk_i2c_init_hw()
634 static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c, in mtk_i2c_get_clk_div_restri() argument
639 if (i2c->dev_comp->ltiming_adjust == 0) in mtk_i2c_get_clk_div_restri()
643 if (i2c->ac_timing.inter_clk_div == 0) in mtk_i2c_get_clk_div_restri()
648 if (i2c->ac_timing.inter_clk_div == 0) in mtk_i2c_get_clk_div_restri()
650 else if (i2c->ac_timing.inter_clk_div == 1) in mtk_i2c_get_clk_div_restri()
660 * Check and Calculate i2c ac-timing
671 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, in mtk_i2c_check_ac_timing() argument
683 if (!i2c->dev_comp->timing_adjust) in mtk_i2c_check_ac_timing()
686 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_check_ac_timing()
691 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_check_ac_timing()
697 i2c->timing_info.scl_int_delay_ns, clk_ns); in mtk_i2c_check_ac_timing()
726 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_check_ac_timing()
727 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | in mtk_i2c_check_ac_timing()
729 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); in mtk_i2c_check_ac_timing()
730 i2c->ac_timing.ltiming |= (sample_cnt << 12) | in mtk_i2c_check_ac_timing()
732 i2c->ac_timing.ext &= ~GENMASK(7, 1); in mtk_i2c_check_ac_timing()
733 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); in mtk_i2c_check_ac_timing()
735 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | in mtk_i2c_check_ac_timing()
737 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | in mtk_i2c_check_ac_timing()
740 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); in mtk_i2c_check_ac_timing()
741 i2c->ac_timing.sda_timing |= (1 << 12) | in mtk_i2c_check_ac_timing()
744 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_check_ac_timing()
745 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); in mtk_i2c_check_ac_timing()
746 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); in mtk_i2c_check_ac_timing()
747 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); in mtk_i2c_check_ac_timing()
749 i2c->ac_timing.scl_hl_ratio = (1 << 12) | in mtk_i2c_check_ac_timing()
751 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | in mtk_i2c_check_ac_timing()
755 i2c->ac_timing.sda_timing = (1 << 12) | in mtk_i2c_check_ac_timing()
763 * Calculate i2c port speed
770 * less than or equal to i2c->speed_hz. The calculation try to get
773 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, in mtk_i2c_calculate_speed() argument
805 clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt); in mtk_i2c_calculate_speed()
812 ret = mtk_i2c_check_ac_timing(i2c, clk_src, in mtk_i2c_calculate_speed()
836 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); in mtk_i2c_calculate_speed()
846 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) in mtk_i2c_set_speed() argument
858 target_speed = i2c->speed_hz; in mtk_i2c_set_speed()
859 parent_clk /= i2c->clk_src_div; in mtk_i2c_set_speed()
861 if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust) in mtk_i2c_set_speed()
863 else if (i2c->dev_comp->timing_adjust) in mtk_i2c_set_speed()
870 i2c->ac_timing.inter_clk_div = clk_div - 1; in mtk_i2c_set_speed()
874 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
881 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; in mtk_i2c_set_speed()
884 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
890 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | in mtk_i2c_set_speed()
893 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_set_speed()
894 i2c->ltiming_reg = in mtk_i2c_set_speed()
898 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
904 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; in mtk_i2c_set_speed()
907 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; in mtk_i2c_set_speed()
909 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_set_speed()
910 i2c->ltiming_reg = in mtk_i2c_set_speed()
921 static void i2c_dump_register(struct mtk_i2c *i2c) in i2c_dump_register() argument
923 dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", in i2c_dump_register()
924 mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), in i2c_dump_register()
925 mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); in i2c_dump_register()
926 dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", in i2c_dump_register()
927 mtk_i2c_readw(i2c, OFFSET_INTR_STAT), in i2c_dump_register()
928 mtk_i2c_readw(i2c, OFFSET_CONTROL)); in i2c_dump_register()
929 dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n", in i2c_dump_register()
930 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), in i2c_dump_register()
931 mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); in i2c_dump_register()
932 dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n", in i2c_dump_register()
933 mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), in i2c_dump_register()
934 mtk_i2c_readw(i2c, OFFSET_TIMING)); in i2c_dump_register()
935 dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n", in i2c_dump_register()
936 mtk_i2c_readw(i2c, OFFSET_START), in i2c_dump_register()
937 mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); in i2c_dump_register()
938 dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n", in i2c_dump_register()
939 mtk_i2c_readw(i2c, OFFSET_HS), in i2c_dump_register()
940 mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); in i2c_dump_register()
941 dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n", in i2c_dump_register()
942 mtk_i2c_readw(i2c, OFFSET_DCM_EN), in i2c_dump_register()
943 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); in i2c_dump_register()
944 dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n", in i2c_dump_register()
945 mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), in i2c_dump_register()
946 mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); in i2c_dump_register()
947 dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n", in i2c_dump_register()
948 mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), in i2c_dump_register()
949 mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); in i2c_dump_register()
950 if (i2c->dev_comp->regs == mt_i2c_regs_v2) { in i2c_dump_register()
951 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n", in i2c_dump_register()
952 mtk_i2c_readw(i2c, OFFSET_LTIMING), in i2c_dump_register()
953 mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); in i2c_dump_register()
955 dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n", in i2c_dump_register()
956 readl(i2c->pdmabase + OFFSET_INT_FLAG), in i2c_dump_register()
957 readl(i2c->pdmabase + OFFSET_INT_EN)); in i2c_dump_register()
958 dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n", in i2c_dump_register()
959 readl(i2c->pdmabase + OFFSET_EN), in i2c_dump_register()
960 readl(i2c->pdmabase + OFFSET_CON)); in i2c_dump_register()
961 dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n", in i2c_dump_register()
962 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), in i2c_dump_register()
963 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); in i2c_dump_register()
964 dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n", in i2c_dump_register()
965 readl(i2c->pdmabase + OFFSET_TX_LEN), in i2c_dump_register()
966 readl(i2c->pdmabase + OFFSET_RX_LEN)); in i2c_dump_register()
967 dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x", in i2c_dump_register()
968 readl(i2c->pdmabase + OFFSET_TX_4G_MODE), in i2c_dump_register()
969 readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); in i2c_dump_register()
972 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, in mtk_i2c_do_transfer() argument
988 i2c->irq_stat = 0; in mtk_i2c_do_transfer()
990 if (i2c->auto_restart) in mtk_i2c_do_transfer()
993 reinit_completion(&i2c->msg_complete); in mtk_i2c_do_transfer()
995 if (i2c->dev_comp->apdma_sync && in mtk_i2c_do_transfer()
996 i2c->op != I2C_MASTER_WRRD && num > 1) { in mtk_i2c_do_transfer()
997 mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL); in mtk_i2c_do_transfer()
999 i2c->pdmabase + OFFSET_RST); in mtk_i2c_do_transfer()
1001 ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, in mtk_i2c_do_transfer()
1006 dev_err(i2c->dev, "DMA warm reset timeout\n"); in mtk_i2c_do_transfer()
1010 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_do_transfer()
1011 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); in mtk_i2c_do_transfer()
1012 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); in mtk_i2c_do_transfer()
1013 mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, in mtk_i2c_do_transfer()
1017 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & in mtk_i2c_do_transfer()
1019 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) in mtk_i2c_do_transfer()
1022 if (i2c->op == I2C_MASTER_WRRD) in mtk_i2c_do_transfer()
1025 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_do_transfer()
1028 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); in mtk_i2c_do_transfer()
1031 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
1034 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); in mtk_i2c_do_transfer()
1037 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
1041 if (i2c->op == I2C_MASTER_WRRD) { in mtk_i2c_do_transfer()
1042 if (i2c->dev_comp->aux_len_reg) { in mtk_i2c_do_transfer()
1043 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); in mtk_i2c_do_transfer()
1044 mtk_i2c_writew(i2c, (msgs + 1)->len, in mtk_i2c_do_transfer()
1047 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, in mtk_i2c_do_transfer()
1050 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); in mtk_i2c_do_transfer()
1052 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); in mtk_i2c_do_transfer()
1053 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); in mtk_i2c_do_transfer()
1056 if (i2c->dev_comp->apdma_sync) { in mtk_i2c_do_transfer()
1058 if (i2c->op == I2C_MASTER_WRRD) in mtk_i2c_do_transfer()
1063 if (i2c->op == I2C_MASTER_RD) { in mtk_i2c_do_transfer()
1064 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
1065 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
1071 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, in mtk_i2c_do_transfer()
1073 if (dma_mapping_error(i2c->dev, rpaddr)) { in mtk_i2c_do_transfer()
1079 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
1081 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); in mtk_i2c_do_transfer()
1084 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); in mtk_i2c_do_transfer()
1085 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); in mtk_i2c_do_transfer()
1086 } else if (i2c->op == I2C_MASTER_WR) { in mtk_i2c_do_transfer()
1087 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
1088 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
1094 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, in mtk_i2c_do_transfer()
1096 if (dma_mapping_error(i2c->dev, wpaddr)) { in mtk_i2c_do_transfer()
1102 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
1104 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); in mtk_i2c_do_transfer()
1107 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); in mtk_i2c_do_transfer()
1108 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); in mtk_i2c_do_transfer()
1110 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
1111 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
1117 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, in mtk_i2c_do_transfer()
1119 if (dma_mapping_error(i2c->dev, wpaddr)) { in mtk_i2c_do_transfer()
1127 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
1135 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, in mtk_i2c_do_transfer()
1138 if (dma_mapping_error(i2c->dev, rpaddr)) { in mtk_i2c_do_transfer()
1139 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
1148 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
1150 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); in mtk_i2c_do_transfer()
1153 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); in mtk_i2c_do_transfer()
1156 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); in mtk_i2c_do_transfer()
1157 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); in mtk_i2c_do_transfer()
1158 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); in mtk_i2c_do_transfer()
1159 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); in mtk_i2c_do_transfer()
1162 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); in mtk_i2c_do_transfer()
1164 if (!i2c->auto_restart) { in mtk_i2c_do_transfer()
1171 mtk_i2c_writew(i2c, start_reg, OFFSET_START); in mtk_i2c_do_transfer()
1173 ret = wait_for_completion_timeout(&i2c->msg_complete, in mtk_i2c_do_transfer()
1174 i2c->adap.timeout); in mtk_i2c_do_transfer()
1177 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
1180 if (i2c->op == I2C_MASTER_WR) { in mtk_i2c_do_transfer()
1181 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
1185 } else if (i2c->op == I2C_MASTER_RD) { in mtk_i2c_do_transfer()
1186 dma_unmap_single(i2c->dev, rpaddr, in mtk_i2c_do_transfer()
1191 dma_unmap_single(i2c->dev, wpaddr, msgs->len, in mtk_i2c_do_transfer()
1193 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, in mtk_i2c_do_transfer()
1201 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); in mtk_i2c_do_transfer()
1202 i2c_dump_register(i2c); in mtk_i2c_do_transfer()
1203 mtk_i2c_init_hw(i2c); in mtk_i2c_do_transfer()
1207 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { in mtk_i2c_do_transfer()
1208 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); in mtk_i2c_do_transfer()
1209 mtk_i2c_init_hw(i2c); in mtk_i2c_do_transfer()
1221 struct mtk_i2c *i2c = i2c_get_adapdata(adap); in mtk_i2c_transfer() local
1223 ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_transfer()
1227 i2c->auto_restart = i2c->dev_comp->auto_restart; in mtk_i2c_transfer()
1230 if (i2c->auto_restart && num == 2) { in mtk_i2c_transfer()
1233 i2c->auto_restart = 0; in mtk_i2c_transfer()
1237 if (i2c->auto_restart && num >= 2 && in mtk_i2c_transfer()
1238 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) in mtk_i2c_transfer()
1242 i2c->ignore_restart_irq = true; in mtk_i2c_transfer()
1244 i2c->ignore_restart_irq = false; in mtk_i2c_transfer()
1248 dev_dbg(i2c->dev, "data buffer is NULL.\n"); in mtk_i2c_transfer()
1254 i2c->op = I2C_MASTER_RD; in mtk_i2c_transfer()
1256 i2c->op = I2C_MASTER_WR; in mtk_i2c_transfer()
1258 if (!i2c->auto_restart) { in mtk_i2c_transfer()
1261 i2c->op = I2C_MASTER_WRRD; in mtk_i2c_transfer()
1267 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); in mtk_i2c_transfer()
1277 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_transfer()
1283 struct mtk_i2c *i2c = dev_id; in mtk_i2c_irq() local
1287 if (i2c->auto_restart) in mtk_i2c_irq()
1290 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); in mtk_i2c_irq()
1291 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); in mtk_i2c_irq()
1294 * when occurs ack error, i2c controller generate two interrupts in mtk_i2c_irq()
1296 * i2c->irq_stat need keep the two interrupt value. in mtk_i2c_irq()
1298 i2c->irq_stat |= intr_stat; in mtk_i2c_irq()
1300 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { in mtk_i2c_irq()
1301 i2c->ignore_restart_irq = false; in mtk_i2c_irq()
1302 i2c->irq_stat = 0; in mtk_i2c_irq()
1303 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | in mtk_i2c_irq()
1306 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) in mtk_i2c_irq()
1307 complete(&i2c->msg_complete); in mtk_i2c_irq()
1327 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) in mtk_i2c_parse_dt() argument
1331 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); in mtk_i2c_parse_dt()
1333 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; in mtk_i2c_parse_dt()
1335 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); in mtk_i2c_parse_dt()
1339 if (i2c->clk_src_div == 0) in mtk_i2c_parse_dt()
1342 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); in mtk_i2c_parse_dt()
1343 i2c->use_push_pull = in mtk_i2c_parse_dt()
1346 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true); in mtk_i2c_parse_dt()
1354 struct mtk_i2c *i2c; in mtk_i2c_probe() local
1358 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in mtk_i2c_probe()
1359 if (!i2c) in mtk_i2c_probe()
1363 i2c->base = devm_ioremap_resource(&pdev->dev, res); in mtk_i2c_probe()
1364 if (IS_ERR(i2c->base)) in mtk_i2c_probe()
1365 return PTR_ERR(i2c->base); in mtk_i2c_probe()
1368 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); in mtk_i2c_probe()
1369 if (IS_ERR(i2c->pdmabase)) in mtk_i2c_probe()
1370 return PTR_ERR(i2c->pdmabase); in mtk_i2c_probe()
1376 init_completion(&i2c->msg_complete); in mtk_i2c_probe()
1378 i2c->dev_comp = of_device_get_match_data(&pdev->dev); in mtk_i2c_probe()
1379 i2c->adap.dev.of_node = pdev->dev.of_node; in mtk_i2c_probe()
1380 i2c->dev = &pdev->dev; in mtk_i2c_probe()
1381 i2c->adap.dev.parent = &pdev->dev; in mtk_i2c_probe()
1382 i2c->adap.owner = THIS_MODULE; in mtk_i2c_probe()
1383 i2c->adap.algo = &mtk_i2c_algorithm; in mtk_i2c_probe()
1384 i2c->adap.quirks = i2c->dev_comp->quirks; in mtk_i2c_probe()
1385 i2c->adap.timeout = 2 * HZ; in mtk_i2c_probe()
1386 i2c->adap.retries = 1; in mtk_i2c_probe()
1387 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus"); in mtk_i2c_probe()
1388 if (IS_ERR(i2c->adap.bus_regulator)) { in mtk_i2c_probe()
1389 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV) in mtk_i2c_probe()
1390 i2c->adap.bus_regulator = NULL; in mtk_i2c_probe()
1392 return PTR_ERR(i2c->adap.bus_regulator); in mtk_i2c_probe()
1395 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); in mtk_i2c_probe()
1399 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) in mtk_i2c_probe()
1404 i2c->clocks[i].id = i2c_mt65xx_clk_ids[i]; in mtk_i2c_probe()
1407 i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main"); in mtk_i2c_probe()
1408 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) { in mtk_i2c_probe()
1410 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk); in mtk_i2c_probe()
1413 i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma"); in mtk_i2c_probe()
1414 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) { in mtk_i2c_probe()
1416 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk); in mtk_i2c_probe()
1419 i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb"); in mtk_i2c_probe()
1420 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) in mtk_i2c_probe()
1421 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); in mtk_i2c_probe()
1423 if (i2c->have_pmic) { in mtk_i2c_probe()
1424 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); in mtk_i2c_probe()
1425 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { in mtk_i2c_probe()
1427 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); in mtk_i2c_probe()
1431 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; in mtk_i2c_probe()
1435 strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); in mtk_i2c_probe()
1437 ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); in mtk_i2c_probe()
1443 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_probe()
1445 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); in mtk_i2c_probe()
1452 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_probe()
1457 mtk_i2c_init_hw(i2c); in mtk_i2c_probe()
1458 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_probe()
1462 dev_name(&pdev->dev), i2c); in mtk_i2c_probe()
1465 "Request I2C IRQ %d fail\n", irq); in mtk_i2c_probe()
1469 i2c_set_adapdata(&i2c->adap, i2c); in mtk_i2c_probe()
1470 ret = i2c_add_adapter(&i2c->adap); in mtk_i2c_probe()
1474 platform_set_drvdata(pdev, i2c); in mtk_i2c_probe()
1479 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_probe()
1486 struct mtk_i2c *i2c = platform_get_drvdata(pdev); in mtk_i2c_remove() local
1488 i2c_del_adapter(&i2c->adap); in mtk_i2c_remove()
1490 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_remove()
1498 struct mtk_i2c *i2c = dev_get_drvdata(dev); in mtk_i2c_suspend_noirq() local
1500 i2c_mark_adapter_suspended(&i2c->adap); in mtk_i2c_suspend_noirq()
1501 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_suspend_noirq()
1509 struct mtk_i2c *i2c = dev_get_drvdata(dev); in mtk_i2c_resume_noirq() local
1511 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_resume_noirq()
1517 mtk_i2c_init_hw(i2c); in mtk_i2c_resume_noirq()
1519 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_resume_noirq()
1521 i2c_mark_adapter_resumed(&i2c->adap); in mtk_i2c_resume_noirq()
1545 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");