1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/bits.h>
93 	/* Intermediates for recording the transfer process */
112 	writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK);  in hisi_i2c_enable_int()
117 	writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK);  in hisi_i2c_disable_int()
122 	writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR);  in hisi_i2c_clear_int()
127 	u32 int_err = ctlr->xfer_err, reg;  in hisi_i2c_handle_errors()
130 		reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);  in hisi_i2c_handle_errors()
133 			dev_err(ctlr->dev, "rx fifo error read\n");  in hisi_i2c_handle_errors()
136 			dev_err(ctlr->dev, "rx fifo error write\n");  in hisi_i2c_handle_errors()
139 			dev_err(ctlr->dev, "tx fifo error read\n");  in hisi_i2c_handle_errors()
142 			dev_err(ctlr->dev, "tx fifo error write\n");  in hisi_i2c_handle_errors()
148 	struct i2c_msg *msg = ctlr->msgs;  in hisi_i2c_start_xfer()
151 	reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL);  in hisi_i2c_start_xfer()
153 	if (msg->flags & I2C_M_TEN)  in hisi_i2c_start_xfer()
155 	writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);  in hisi_i2c_start_xfer()
157 	reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR);  in hisi_i2c_start_xfer()
159 	reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr);  in hisi_i2c_start_xfer()
160 	writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR);  in hisi_i2c_start_xfer()
162 	reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL);  in hisi_i2c_start_xfer()
164 	writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);  in hisi_i2c_start_xfer()
166 	writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);  in hisi_i2c_start_xfer()
176 	ctlr->msg_num = 0;  in hisi_i2c_reset_xfer()
177 	ctlr->xfer_err = 0;  in hisi_i2c_reset_xfer()
178 	ctlr->msg_tx_idx = 0;  in hisi_i2c_reset_xfer()
179 	ctlr->msg_rx_idx = 0;  in hisi_i2c_reset_xfer()
180 	ctlr->buf_tx_idx = 0;  in hisi_i2c_reset_xfer()
181 	ctlr->buf_rx_idx = 0;  in hisi_i2c_reset_xfer()
185  * Initialize the transfer information and start the I2C bus transfer.
186  * We only configure the transfer and do some pre/post works here, and
187  * wait for the transfer done. The major transfer process is performed
191 				int num)  in hisi_i2c_master_xfer()  argument
195 	int ret = num;  in hisi_i2c_master_xfer()
198 	ctlr->completion = &done;  in hisi_i2c_master_xfer()
199 	ctlr->msg_num = num;  in hisi_i2c_master_xfer()
200 	ctlr->msgs = msgs;  in hisi_i2c_master_xfer()
204 	if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) {  in hisi_i2c_master_xfer()
206 		synchronize_irq(ctlr->irq);  in hisi_i2c_master_xfer()
207 		i2c_recover_bus(&ctlr->adapter);  in hisi_i2c_master_xfer()
208 		dev_err(ctlr->dev, "bus transfer timeout\n");  in hisi_i2c_master_xfer()
209 		ret = -EIO;  in hisi_i2c_master_xfer()
212 	if (ctlr->xfer_err) {  in hisi_i2c_master_xfer()
214 		ret = -EIO;  in hisi_i2c_master_xfer()
218 	ctlr->completion = NULL;  in hisi_i2c_master_xfer()
238 	while (ctlr->msg_rx_idx < ctlr->msg_num) {  in hisi_i2c_read_rx_fifo()
239 		cur_msg = ctlr->msgs + ctlr->msg_rx_idx;  in hisi_i2c_read_rx_fifo()
241 		if (!(cur_msg->flags & I2C_M_RD)) {  in hisi_i2c_read_rx_fifo()
242 			ctlr->msg_rx_idx++;  in hisi_i2c_read_rx_fifo()
246 		fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);  in hisi_i2c_read_rx_fifo()
248 		       ctlr->buf_rx_idx < cur_msg->len) {  in hisi_i2c_read_rx_fifo()
249 			cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA);  in hisi_i2c_read_rx_fifo()
250 			fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);  in hisi_i2c_read_rx_fifo()
253 		if (ctlr->buf_rx_idx == cur_msg->len) {  in hisi_i2c_read_rx_fifo()
254 			ctlr->buf_rx_idx = 0;  in hisi_i2c_read_rx_fifo()
255 			ctlr->msg_rx_idx++;  in hisi_i2c_read_rx_fifo()
272 	while (ctlr->msg_tx_idx < ctlr->msg_num) {  in hisi_i2c_xfer_msg()
273 		cur_msg = ctlr->msgs + ctlr->msg_tx_idx;  in hisi_i2c_xfer_msg()
274 		last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1);  in hisi_i2c_xfer_msg()
277 		if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx)  in hisi_i2c_xfer_msg()
280 		fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);  in hisi_i2c_xfer_msg()
282 		       ctlr->buf_tx_idx < cur_msg->len && max_write) {  in hisi_i2c_xfer_msg()
291 			if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg)  in hisi_i2c_xfer_msg()
294 			if (cur_msg->flags & I2C_M_RD)  in hisi_i2c_xfer_msg()
298 						  cur_msg->buf[ctlr->buf_tx_idx]);  in hisi_i2c_xfer_msg()
300 			writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA);  in hisi_i2c_xfer_msg()
301 			ctlr->buf_tx_idx++;  in hisi_i2c_xfer_msg()
302 			max_write--;  in hisi_i2c_xfer_msg()
304 			fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);  in hisi_i2c_xfer_msg()
307 		/* Update the transfer index after per message transfer is done. */  in hisi_i2c_xfer_msg()
308 		if (ctlr->buf_tx_idx == cur_msg->len) {  in hisi_i2c_xfer_msg()
309 			ctlr->buf_tx_idx = 0;  in hisi_i2c_xfer_msg()
310 			ctlr->msg_tx_idx++;  in hisi_i2c_xfer_msg()
324 	int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT);  in hisi_i2c_irq()
333 		ctlr->xfer_err = int_stat;  in hisi_i2c_irq()
337 	/* Drain the rx fifo before finish the transfer */  in hisi_i2c_irq()
342 	if (int_stat & HISI_I2C_INT_TRANS_CPLT || ctlr->xfer_err) {  in hisi_i2c_irq()
345 		complete(ctlr->completion);  in hisi_i2c_irq()
365 	total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz);  in hisi_i2c_set_scl()
369 	t_scl_lcnt = total_cnt - t_scl_hcnt;  in hisi_i2c_set_scl()
371 	scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz);  in hisi_i2c_set_scl()
373 	scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz);  in hisi_i2c_set_scl()
376 	scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt;  in hisi_i2c_set_scl()
377 	scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt;  in hisi_i2c_set_scl()
379 	writel(scl_hcnt, ctlr->iobase + reg_hcnt);  in hisi_i2c_set_scl()
380 	writel(scl_lcnt, ctlr->iobase + reg_lcnt);  in hisi_i2c_set_scl()
387 	i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true);  in hisi_i2c_configure_bus()
388 	ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz);  in hisi_i2c_configure_bus()
390 	switch (ctlr->t.bus_freq_hz) {  in hisi_i2c_configure_bus()
404 		ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;  in hisi_i2c_configure_bus()
409 	reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL);  in hisi_i2c_configure_bus()
412 	writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);  in hisi_i2c_configure_bus()
414 	sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz);  in hisi_i2c_configure_bus()
417 	writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD);  in hisi_i2c_configure_bus()
419 	writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN);  in hisi_i2c_configure_bus()
423 	writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);  in hisi_i2c_configure_bus()
429 	struct device *dev = &pdev->dev;  in hisi_i2c_probe()
437 		return -ENOMEM;  in hisi_i2c_probe()
439 	ctlr->iobase = devm_platform_ioremap_resource(pdev, 0);  in hisi_i2c_probe()
440 	if (IS_ERR(ctlr->iobase))  in hisi_i2c_probe()
441 		return PTR_ERR(ctlr->iobase);  in hisi_i2c_probe()
443 	ctlr->irq = platform_get_irq(pdev, 0);  in hisi_i2c_probe()
444 	if (ctlr->irq < 0)  in hisi_i2c_probe()
445 		return ctlr->irq;  in hisi_i2c_probe()
447 	ctlr->dev = dev;  in hisi_i2c_probe()
451 	ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr);  in hisi_i2c_probe()
463 	ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ);  in hisi_i2c_probe()
467 	adapter = &ctlr->adapter;  in hisi_i2c_probe()
468 	snprintf(adapter->name, sizeof(adapter->name),  in hisi_i2c_probe()
470 	adapter->owner = THIS_MODULE;  in hisi_i2c_probe()
471 	adapter->algo = &hisi_i2c_algo;  in hisi_i2c_probe()
472 	adapter->dev.parent = dev;  in hisi_i2c_probe()
479 	hw_version = readl(ctlr->iobase + HISI_I2C_VERSION);  in hisi_i2c_probe()
480 	dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n",  in hisi_i2c_probe()
481 		 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version);  in hisi_i2c_probe()
495 		.name	= "hisi-i2c",