Lines Matching +full:fast +full:- +full:read
1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include "i2c-designware-core.h"
33 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
34 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
37 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
44 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
53 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); in i2c_dw_set_timings_master()
58 /* Set standard and fast speed dividers for high/low periods */ in i2c_dw_set_timings_master()
59 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
60 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
63 if (!dev->ss_hcnt || !dev->ss_lcnt) { in i2c_dw_set_timings_master()
65 dev->ss_hcnt = in i2c_dw_set_timings_master()
71 dev->ss_lcnt = in i2c_dw_set_timings_master()
77 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
78 dev->ss_hcnt, dev->ss_lcnt); in i2c_dw_set_timings_master()
81 * Set SCL timing parameters for fast mode or fast mode plus. Only in i2c_dw_set_timings_master()
85 if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) { in i2c_dw_set_timings_master()
87 * Check are Fast Mode Plus parameters available. Calculate in i2c_dw_set_timings_master()
88 * SCL timing parameters for Fast Mode Plus if not set. in i2c_dw_set_timings_master()
90 if (dev->fp_hcnt && dev->fp_lcnt) { in i2c_dw_set_timings_master()
91 dev->fs_hcnt = dev->fp_hcnt; in i2c_dw_set_timings_master()
92 dev->fs_lcnt = dev->fp_lcnt; in i2c_dw_set_timings_master()
95 dev->fs_hcnt = in i2c_dw_set_timings_master()
101 dev->fs_lcnt = in i2c_dw_set_timings_master()
110 * Calculate SCL timing parameters for fast mode if not set. They are in i2c_dw_set_timings_master()
113 if (!dev->fs_hcnt || !dev->fs_lcnt) { in i2c_dw_set_timings_master()
115 dev->fs_hcnt = in i2c_dw_set_timings_master()
121 dev->fs_lcnt = in i2c_dw_set_timings_master()
127 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
128 fp_str, dev->fs_hcnt, dev->fs_lcnt); in i2c_dw_set_timings_master()
130 /* Check is high speed possible and fall back to fast mode if not */ in i2c_dw_set_timings_master()
131 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == in i2c_dw_set_timings_master()
135 dev_err(dev->dev, "High Speed not supported!\n"); in i2c_dw_set_timings_master()
136 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; in i2c_dw_set_timings_master()
137 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; in i2c_dw_set_timings_master()
138 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_set_timings_master()
139 dev->hs_hcnt = 0; in i2c_dw_set_timings_master()
140 dev->hs_lcnt = 0; in i2c_dw_set_timings_master()
141 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { in i2c_dw_set_timings_master()
143 dev->hs_hcnt = in i2c_dw_set_timings_master()
149 dev->hs_lcnt = in i2c_dw_set_timings_master()
155 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
156 dev->hs_hcnt, dev->hs_lcnt); in i2c_dw_set_timings_master()
163 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); in i2c_dw_set_timings_master()
168 * i2c_dw_init_master() - Initialize the designware I2C master hardware
187 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); in i2c_dw_init_master()
188 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); in i2c_dw_init_master()
190 /* Write fast mode/fast mode plus timing parameters */ in i2c_dw_init_master()
191 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); in i2c_dw_init_master()
192 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); in i2c_dw_init_master()
195 if (dev->hs_hcnt && dev->hs_lcnt) { in i2c_dw_init_master()
196 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); in i2c_dw_init_master()
197 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); in i2c_dw_init_master()
201 if (dev->sda_hold_time) in i2c_dw_init_master()
202 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); in i2c_dw_init_master()
212 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_init()
220 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { in i2c_dw_xfer_init()
223 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing in i2c_dw_xfer_init()
231 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER, in i2c_dw_xfer_init()
235 * Set the slave (target) address and enable 10-bit addressing mode in i2c_dw_xfer_init()
238 regmap_write(dev->map, DW_IC_TAR, in i2c_dw_xfer_init()
239 msgs[dev->msg_write_idx].addr | ic_tar); in i2c_dw_xfer_init()
247 /* Dummy read to avoid the register getting stuck on Bay Trail */ in i2c_dw_xfer_init()
248 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy); in i2c_dw_xfer_init()
251 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); in i2c_dw_xfer_init()
252 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK); in i2c_dw_xfer_init()
260 ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val, in i2c_dw_check_stopbit()
264 dev_err(dev->dev, "i2c timeout error %d\n", ret); in i2c_dw_check_stopbit()
281 * Initiate and continue master read/write transaction with polling
297 regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN); in amd_i2c_dw_xfer_quirk()
299 dev->msgs = msgs; in amd_i2c_dw_xfer_quirk()
300 dev->msgs_num = num_msgs; in amd_i2c_dw_xfer_quirk()
304 /* Initiate messages read/write transaction */ in amd_i2c_dw_xfer_quirk()
310 regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1); in amd_i2c_dw_xfer_quirk()
312 * Initiate the i2c read/write transaction of buffer length, in amd_i2c_dw_xfer_quirk()
316 for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) { in amd_i2c_dw_xfer_quirk()
317 if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1) in amd_i2c_dw_xfer_quirk()
322 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100); in amd_i2c_dw_xfer_quirk()
323 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd); in amd_i2c_dw_xfer_quirk()
325 regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1)); in amd_i2c_dw_xfer_quirk()
326 regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1)); in amd_i2c_dw_xfer_quirk()
330 * when read/write the last byte. in amd_i2c_dw_xfer_quirk()
337 regmap_read(dev->map, DW_IC_DATA_CMD, &val); in amd_i2c_dw_xfer_quirk()
345 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd); in amd_i2c_dw_xfer_quirk()
358 * Initiate (and continue) low level master read/write transaction.
366 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_msg()
369 u32 addr = msgs[dev->msg_write_idx].addr; in i2c_dw_xfer_msg()
370 u32 buf_len = dev->tx_buf_len; in i2c_dw_xfer_msg()
371 u8 *buf = dev->tx_buf; in i2c_dw_xfer_msg()
377 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { in i2c_dw_xfer_msg()
378 u32 flags = msgs[dev->msg_write_idx].flags; in i2c_dw_xfer_msg()
385 if (msgs[dev->msg_write_idx].addr != addr) { in i2c_dw_xfer_msg()
386 dev_err(dev->dev, in i2c_dw_xfer_msg()
388 dev->msg_err = -EINVAL; in i2c_dw_xfer_msg()
392 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { in i2c_dw_xfer_msg()
394 buf = msgs[dev->msg_write_idx].buf; in i2c_dw_xfer_msg()
395 buf_len = msgs[dev->msg_write_idx].len; in i2c_dw_xfer_msg()
401 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && in i2c_dw_xfer_msg()
402 (dev->msg_write_idx > 0)) in i2c_dw_xfer_msg()
406 regmap_read(dev->map, DW_IC_TXFLR, &flr); in i2c_dw_xfer_msg()
407 tx_limit = dev->tx_fifo_depth - flr; in i2c_dw_xfer_msg()
409 regmap_read(dev->map, DW_IC_RXFLR, &flr); in i2c_dw_xfer_msg()
410 rx_limit = dev->rx_fifo_depth - flr; in i2c_dw_xfer_msg()
423 * i2c-core always sets the buffer length of in i2c_dw_xfer_msg()
428 if (dev->msg_write_idx == dev->msgs_num - 1 && in i2c_dw_xfer_msg()
437 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { in i2c_dw_xfer_msg()
440 if (dev->rx_outstanding >= dev->rx_fifo_depth) in i2c_dw_xfer_msg()
443 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
445 rx_limit--; in i2c_dw_xfer_msg()
446 dev->rx_outstanding++; in i2c_dw_xfer_msg()
448 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
451 tx_limit--; buf_len--; in i2c_dw_xfer_msg()
454 dev->tx_buf = buf; in i2c_dw_xfer_msg()
455 dev->tx_buf_len = buf_len; in i2c_dw_xfer_msg()
464 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
467 dev->status &= ~STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
474 if (dev->msg_write_idx == dev->msgs_num) in i2c_dw_xfer_msg()
477 if (dev->msg_err) in i2c_dw_xfer_msg()
480 regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask); in i2c_dw_xfer_msg()
486 struct i2c_msg *msgs = dev->msgs; in i2c_dw_recv_len()
487 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_recv_len()
494 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); in i2c_dw_recv_len()
495 msgs[dev->msg_read_idx].len = len; in i2c_dw_recv_len()
496 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; in i2c_dw_recv_len()
504 struct i2c_msg *msgs = dev->msgs; in i2c_dw_read()
507 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { in i2c_dw_read()
511 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) in i2c_dw_read()
514 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { in i2c_dw_read()
515 len = msgs[dev->msg_read_idx].len; in i2c_dw_read()
516 buf = msgs[dev->msg_read_idx].buf; in i2c_dw_read()
518 len = dev->rx_buf_len; in i2c_dw_read()
519 buf = dev->rx_buf; in i2c_dw_read()
522 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); in i2c_dw_read()
524 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { in i2c_dw_read()
525 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_read()
527 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); in i2c_dw_read()
534 dev->rx_outstanding--; in i2c_dw_read()
538 dev->status |= STATUS_READ_IN_PROGRESS; in i2c_dw_read()
539 dev->rx_buf_len = len; in i2c_dw_read()
540 dev->rx_buf = buf; in i2c_dw_read()
543 dev->status &= ~STATUS_READ_IN_PROGRESS; in i2c_dw_read()
556 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); in i2c_dw_xfer()
558 pm_runtime_get_sync(dev->dev); in i2c_dw_xfer()
565 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) { in i2c_dw_xfer()
570 reinit_completion(&dev->cmd_complete); in i2c_dw_xfer()
571 dev->msgs = msgs; in i2c_dw_xfer()
572 dev->msgs_num = num; in i2c_dw_xfer()
573 dev->cmd_err = 0; in i2c_dw_xfer()
574 dev->msg_write_idx = 0; in i2c_dw_xfer()
575 dev->msg_read_idx = 0; in i2c_dw_xfer()
576 dev->msg_err = 0; in i2c_dw_xfer()
577 dev->status = STATUS_IDLE; in i2c_dw_xfer()
578 dev->abort_source = 0; in i2c_dw_xfer()
579 dev->rx_outstanding = 0; in i2c_dw_xfer()
593 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) { in i2c_dw_xfer()
594 dev_err(dev->dev, "controller timed out\n"); in i2c_dw_xfer()
596 i2c_recover_bus(&dev->adapter); in i2c_dw_xfer()
598 ret = -ETIMEDOUT; in i2c_dw_xfer()
612 if (dev->msg_err) { in i2c_dw_xfer()
613 ret = dev->msg_err; in i2c_dw_xfer()
618 if (likely(!dev->cmd_err && !dev->status)) { in i2c_dw_xfer()
624 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { in i2c_dw_xfer()
629 if (dev->status) in i2c_dw_xfer()
630 dev_err(dev->dev, in i2c_dw_xfer()
631 "transfer terminated early - interrupt latency too high?\n"); in i2c_dw_xfer()
633 ret = -EIO; in i2c_dw_xfer()
639 pm_runtime_mark_last_busy(dev->dev); in i2c_dw_xfer()
640 pm_runtime_put_autosuspend(dev->dev); in i2c_dw_xfer()
670 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); in i2c_dw_read_clear_intrbits()
677 * Instead, use the separately-prepared IC_CLR_* registers. in i2c_dw_read_clear_intrbits()
680 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); in i2c_dw_read_clear_intrbits()
682 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
684 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
686 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy); in i2c_dw_read_clear_intrbits()
690 * the IC_CLR_TX_ABRT is read. Preserve it beforehand. in i2c_dw_read_clear_intrbits()
692 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source); in i2c_dw_read_clear_intrbits()
693 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); in i2c_dw_read_clear_intrbits()
696 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); in i2c_dw_read_clear_intrbits()
698 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); in i2c_dw_read_clear_intrbits()
700 ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL))) in i2c_dw_read_clear_intrbits()
701 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); in i2c_dw_read_clear_intrbits()
703 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); in i2c_dw_read_clear_intrbits()
705 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); in i2c_dw_read_clear_intrbits()
720 if (!(dev->status & STATUS_ACTIVE)) { in i2c_dw_irq_handler_master()
728 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in i2c_dw_irq_handler_master()
733 dev->cmd_err |= DW_IC_ERR_TX_ABRT; in i2c_dw_irq_handler_master()
734 dev->status = STATUS_IDLE; in i2c_dw_irq_handler_master()
735 dev->rx_outstanding = 0; in i2c_dw_irq_handler_master()
741 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in i2c_dw_irq_handler_master()
758 if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) && in i2c_dw_irq_handler_master()
759 (dev->rx_outstanding == 0)) in i2c_dw_irq_handler_master()
760 complete(&dev->cmd_complete); in i2c_dw_irq_handler_master()
761 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { in i2c_dw_irq_handler_master()
763 regmap_read(dev->map, DW_IC_INTR_MASK, &stat); in i2c_dw_irq_handler_master()
765 regmap_write(dev->map, DW_IC_INTR_MASK, stat); in i2c_dw_irq_handler_master()
776 regmap_read(dev->map, DW_IC_ENABLE, &enabled); in i2c_dw_isr()
777 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); in i2c_dw_isr()
778 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); in i2c_dw_isr()
789 struct i2c_timings *t = &dev->timings; in i2c_dw_configure_master()
791 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; in i2c_dw_configure_master()
793 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | in i2c_dw_configure_master()
796 dev->mode = DW_IC_MASTER; in i2c_dw_configure_master()
798 switch (t->bus_freq_hz) { in i2c_dw_configure_master()
800 dev->master_cfg |= DW_IC_CON_SPEED_STD; in i2c_dw_configure_master()
803 dev->master_cfg |= DW_IC_CON_SPEED_HIGH; in i2c_dw_configure_master()
806 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_configure_master()
816 reset_control_assert(dev->rst); in i2c_dw_prepare_recovery()
825 reset_control_deassert(dev->rst); in i2c_dw_unprepare_recovery()
831 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; in i2c_dw_init_recovery_info()
832 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_init_recovery_info()
835 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH); in i2c_dw_init_recovery_info()
839 rinfo->scl_gpiod = gpio; in i2c_dw_init_recovery_info()
841 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); in i2c_dw_init_recovery_info()
844 rinfo->sda_gpiod = gpio; in i2c_dw_init_recovery_info()
846 rinfo->recover_bus = i2c_generic_scl_recovery; in i2c_dw_init_recovery_info()
847 rinfo->prepare_recovery = i2c_dw_prepare_recovery; in i2c_dw_init_recovery_info()
848 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; in i2c_dw_init_recovery_info()
849 adap->bus_recovery_info = rinfo; in i2c_dw_init_recovery_info()
851 dev_info(dev->dev, "running with gpio recovery mode! scl%s", in i2c_dw_init_recovery_info()
852 rinfo->sda_gpiod ? ",sda" : ""); in i2c_dw_init_recovery_info()
859 struct i2c_adapter *adap = &dev->adapter; in amd_i2c_adap_quirk()
862 pm_runtime_get_noresume(dev->dev); in amd_i2c_adap_quirk()
865 dev_err(dev->dev, "Failed to add adapter: %d\n", ret); in amd_i2c_adap_quirk()
866 pm_runtime_put_noidle(dev->dev); in amd_i2c_adap_quirk()
873 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_probe_master()
877 init_completion(&dev->cmd_complete); in i2c_dw_probe_master()
879 dev->init = i2c_dw_init_master; in i2c_dw_probe_master()
880 dev->disable = i2c_dw_disable; in i2c_dw_probe_master()
881 dev->disable_int = i2c_dw_disable_int; in i2c_dw_probe_master()
895 ret = dev->init(dev); in i2c_dw_probe_master()
899 snprintf(adap->name, sizeof(adap->name), in i2c_dw_probe_master()
901 adap->retries = 3; in i2c_dw_probe_master()
902 adap->algo = &i2c_dw_algo; in i2c_dw_probe_master()
903 adap->quirks = &i2c_dw_quirks; in i2c_dw_probe_master()
904 adap->dev.parent = dev->dev; in i2c_dw_probe_master()
907 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) in i2c_dw_probe_master()
910 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { in i2c_dw_probe_master()
923 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags, in i2c_dw_probe_master()
924 dev_name(dev->dev), dev); in i2c_dw_probe_master()
926 dev_err(dev->dev, "failure requesting irq %i: %d\n", in i2c_dw_probe_master()
927 dev->irq, ret); in i2c_dw_probe_master()
941 pm_runtime_get_noresume(dev->dev); in i2c_dw_probe_master()
944 dev_err(dev->dev, "failure adding adapter: %d\n", ret); in i2c_dw_probe_master()
945 pm_runtime_put_noidle(dev->dev); in i2c_dw_probe_master()