Lines Matching +full:0 +full:x0810
26 #define HISI_PTT_TUNING_CTRL 0x0000
27 #define HISI_PTT_TUNING_CTRL_CODE GENMASK(15, 0)
29 #define HISI_PTT_TUNING_DATA 0x0004
30 #define HISI_PTT_TUNING_DATA_VAL_MASK GENMASK(15, 0)
31 #define HISI_PTT_TRACE_ADDR_SIZE 0x0800
32 #define HISI_PTT_TRACE_ADDR_BASE_LO_0 0x0810
33 #define HISI_PTT_TRACE_ADDR_BASE_HI_0 0x0814
34 #define HISI_PTT_TRACE_ADDR_STRIDE 0x8
35 #define HISI_PTT_TRACE_CTRL 0x0850
36 #define HISI_PTT_TRACE_CTRL_EN BIT(0)
43 #define HISI_PTT_TRACE_INT_STAT 0x0890
44 #define HISI_PTT_TRACE_INT_STAT_MASK GENMASK(3, 0)
45 #define HISI_PTT_TRACE_INT_MASK 0x0894
46 #define HISI_PTT_TUNING_INT_STAT 0x0898
47 #define HISI_PTT_TUNING_INT_STAT_MASK BIT(0)
48 #define HISI_PTT_TRACE_WR_STS 0x08a0
49 #define HISI_PTT_TRACE_WR_STS_WRITE GENMASK(27, 0)
51 #define HISI_PTT_TRACE_STS 0x08b0
52 #define HISI_PTT_TRACE_IDLE BIT(0)
53 #define HISI_PTT_DEVICE_RANGE 0x0fe0
55 #define HISI_PTT_DEVICE_RANGE_LOWER GENMASK(15, 0)
56 #define HISI_PTT_LOCATION 0x0fe8
57 #define HISI_PTT_CORE_ID GENMASK(15, 0)
61 #define HISI_PTT_TRACE_DMA_IRQ 0
74 #define HISI_PCIE_CORE_PORT_ID(devfn) ((PCI_SLOT(devfn) & 0x7) << 1)
78 #define HISI_PTT_PMU_FILTER_VAL_MASK GENMASK(15, 0)