Lines Matching +full:tegra194 +full:- +full:gte +full:- +full:lic
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 NVIDIA Corporation
29 #define NV_AON_SLICE_INVALID -1
77 #define HTE_SLICE_SIZE (HTE_SLICE1_TETEN - HTE_SLICE0_TETEN)
239 return readl(hte->regs + reg); in tegra_hte_readl()
245 writel(val, hte->regs + reg); in tegra_hte_writel()
255 return -EINVAL; in tegra_hte_map_to_line_id()
257 return -EINVAL; in tegra_hte_map_to_line_id()
278 return -EINVAL; in tegra_hte_line_xlate()
281 if (gc->of_hte_n_cells < 1) in tegra_hte_line_xlate()
282 return -EINVAL; in tegra_hte_line_xlate()
284 if (args->args_count != gc->of_hte_n_cells) in tegra_hte_line_xlate()
285 return -EINVAL; in tegra_hte_line_xlate()
287 desc->attr.line_id = args->args[0]; in tegra_hte_line_xlate()
290 gs = gc->data; in tegra_hte_line_xlate()
291 if (!gs || !gs->prov_data) in tegra_hte_line_xlate()
292 return -EINVAL; in tegra_hte_line_xlate()
297 * 1) The consumer (gpiolib-cdev for example) which uses GPIO global in tegra_hte_line_xlate()
303 * HTE/GTE namespace. in tegra_hte_line_xlate()
305 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && !args) { in tegra_hte_line_xlate()
306 line_id = desc->attr.line_id - gs->c->base; in tegra_hte_line_xlate()
307 map = gs->prov_data->map; in tegra_hte_line_xlate()
308 map_sz = gs->prov_data->map_sz; in tegra_hte_line_xlate()
309 } else if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && args) { in tegra_hte_line_xlate()
310 line_id = desc->attr.line_id; in tegra_hte_line_xlate()
311 map = gs->prov_data->sec_map; in tegra_hte_line_xlate()
312 map_sz = gs->prov_data->sec_map_sz; in tegra_hte_line_xlate()
314 line_id = desc->attr.line_id; in tegra_hte_line_xlate()
319 dev_err(gc->dev, "line_id:%u mapping failed\n", in tegra_hte_line_xlate()
320 desc->attr.line_id); in tegra_hte_line_xlate()
324 if (*xlated_id > gc->nlines) in tegra_hte_line_xlate()
325 return -EINVAL; in tegra_hte_line_xlate()
327 dev_dbg(gc->dev, "requested id:%u, xlated id:%u\n", in tegra_hte_line_xlate()
328 desc->attr.line_id, *xlated_id); in tegra_hte_line_xlate()
347 return -EINVAL; in tegra_hte_en_dis_common()
349 gs = chip->data; in tegra_hte_en_dis_common()
351 if (line_id > chip->nlines) { in tegra_hte_en_dis_common()
352 dev_err(chip->dev, in tegra_hte_en_dis_common()
355 return -EINVAL; in tegra_hte_en_dis_common()
359 line_bit = line_id & (HTE_SLICE_SIZE - 1); in tegra_hte_en_dis_common()
362 spin_lock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
364 if (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) { in tegra_hte_en_dis_common()
365 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
366 dev_dbg(chip->dev, "device suspended"); in tegra_hte_en_dis_common()
367 return -EBUSY; in tegra_hte_en_dis_common()
377 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
379 dev_dbg(chip->dev, "line: %u, slice %u, line_bit %u, reg:0x%x\n", in tegra_hte_en_dis_common()
388 return -EINVAL; in tegra_hte_enable()
396 return -EINVAL; in tegra_hte_disable()
408 if (!chip || !chip->data || !desc) in tegra_hte_request()
409 return -EINVAL; in tegra_hte_request()
411 gs = chip->data; in tegra_hte_request()
412 attr = &desc->attr; in tegra_hte_request()
414 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_request()
415 if (!attr->line_data) in tegra_hte_request()
416 return -EINVAL; in tegra_hte_request()
418 ret = gpiod_enable_hw_timestamp_ns(attr->line_data, in tegra_hte_request()
419 attr->edge_flags); in tegra_hte_request()
423 gs->line_data[line_id].data = attr->line_data; in tegra_hte_request()
424 gs->line_data[line_id].flags = attr->edge_flags; in tegra_hte_request()
437 if (!chip || !chip->data || !desc) in tegra_hte_release()
438 return -EINVAL; in tegra_hte_release()
440 gs = chip->data; in tegra_hte_release()
441 attr = &desc->attr; in tegra_hte_release()
443 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_release()
444 ret = gpiod_disable_hw_timestamp_ns(attr->line_data, in tegra_hte_release()
445 gs->line_data[line_id].flags); in tegra_hte_release()
449 gs->line_data[line_id].data = NULL; in tegra_hte_release()
450 gs->line_data[line_id].flags = 0; in tegra_hte_release()
462 return -EINVAL; in tegra_hte_clk_src_info()
464 ci->hz = HTE_TS_CLK_RATE_HZ; in tegra_hte_clk_src_info()
465 ci->type = CLOCK_MONOTONIC; in tegra_hte_clk_src_info()
474 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_get_level()
475 desc = gs->line_data[line_id].data; in tegra_hte_get_level()
480 return -1; in tegra_hte_get_level()
508 hte_push_ts_ns(gs->chip, line_id, &el); in tegra_hte_read_fifo()
528 struct tegra_hte_soc *hte_dev = chip->data; in tegra_hte_match_from_linedata()
530 if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO)) in tegra_hte_match_from_linedata()
533 return hte_dev->c == gpiod_to_chip(hdesc->attr.line_data); in tegra_hte_match_from_linedata()
537 { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte},
538 { .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte},
554 struct tegra_hte_soc *gs = dev_get_drvdata(&pdev->dev); in tegra_gte_disable()
561 return !strcmp(chip->label, data); in tegra_get_gpiochip_from_name()
573 dev = &pdev->dev; in tegra_hte_probe()
575 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); in tegra_hte_probe()
578 return -EINVAL; in tegra_hte_probe()
584 return -ENOMEM; in tegra_hte_probe()
588 return -ENOMEM; in tegra_hte_probe()
590 dev_set_drvdata(&pdev->dev, hte_dev); in tegra_hte_probe()
591 hte_dev->prov_data = of_device_get_match_data(&pdev->dev); in tegra_hte_probe()
593 hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_hte_probe()
594 if (IS_ERR(hte_dev->regs)) in tegra_hte_probe()
595 return PTR_ERR(hte_dev->regs); in tegra_hte_probe()
597 ret = of_property_read_u32(dev->of_node, "nvidia,int-threshold", in tegra_hte_probe()
598 &hte_dev->itr_thrshld); in tegra_hte_probe()
600 hte_dev->itr_thrshld = 1; in tegra_hte_probe()
602 hte_dev->sl = devm_kcalloc(dev, slices, sizeof(*hte_dev->sl), in tegra_hte_probe()
604 if (!hte_dev->sl) in tegra_hte_probe()
605 return -ENOMEM; in tegra_hte_probe()
612 hte_dev->hte_irq = ret; in tegra_hte_probe()
613 ret = devm_request_irq(dev, hte_dev->hte_irq, tegra_hte_isr, 0, in tegra_hte_probe()
620 gc->nlines = nlines; in tegra_hte_probe()
621 gc->ops = &g_ops; in tegra_hte_probe()
622 gc->dev = dev; in tegra_hte_probe()
623 gc->data = hte_dev; in tegra_hte_probe()
624 gc->xlate_of = tegra_hte_line_xlate; in tegra_hte_probe()
625 gc->xlate_plat = tegra_hte_line_xlate_plat; in tegra_hte_probe()
626 gc->of_hte_n_cells = 1; in tegra_hte_probe()
628 if (hte_dev->prov_data && in tegra_hte_probe()
629 hte_dev->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_probe()
630 hte_dev->line_data = devm_kcalloc(dev, nlines, in tegra_hte_probe()
631 sizeof(*hte_dev->line_data), in tegra_hte_probe()
633 if (!hte_dev->line_data) in tegra_hte_probe()
634 return -ENOMEM; in tegra_hte_probe()
636 gc->match_from_linedata = tegra_hte_match_from_linedata; in tegra_hte_probe()
638 hte_dev->c = gpiochip_find("tegra194-gpio-aon", in tegra_hte_probe()
640 if (!hte_dev->c) in tegra_hte_probe()
641 return dev_err_probe(dev, -EPROBE_DEFER, in tegra_hte_probe()
645 hte_dev->chip = gc; in tegra_hte_probe()
647 ret = devm_hte_register_chip(hte_dev->chip); in tegra_hte_probe()
649 dev_err(gc->dev, "hte chip register failed"); in tegra_hte_probe()
654 hte_dev->sl[i].flags = 0; in tegra_hte_probe()
655 spin_lock_init(&hte_dev->sl[i].s_lock); in tegra_hte_probe()
660 (hte_dev->itr_thrshld << HTE_TECTRL_OCCU_SHIFT); in tegra_hte_probe()
663 ret = devm_add_action_or_reset(&pdev->dev, tegra_gte_disable, pdev); in tegra_hte_probe()
667 dev_dbg(gc->dev, "lines: %d, slices:%d", gc->nlines, slices); in tegra_hte_probe()
676 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; in tegra_hte_resume_early()
679 tegra_hte_writel(gs, HTE_TECTRL, gs->conf_rval); in tegra_hte_resume_early()
682 spin_lock(&gs->sl[i].s_lock); in tegra_hte_resume_early()
685 gs->sl[i].r_val); in tegra_hte_resume_early()
686 clear_bit(HTE_SUSPEND, &gs->sl[i].flags); in tegra_hte_resume_early()
687 spin_unlock(&gs->sl[i].s_lock); in tegra_hte_resume_early()
697 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; in tegra_hte_suspend_late()
700 gs->conf_rval = tegra_hte_readl(gs, HTE_TECTRL); in tegra_hte_suspend_late()
702 spin_lock(&gs->sl[i].s_lock); in tegra_hte_suspend_late()
703 gs->sl[i].r_val = tegra_hte_readl(gs, in tegra_hte_suspend_late()
705 set_bit(HTE_SUSPEND, &gs->sl[i].flags); in tegra_hte_suspend_late()
706 spin_unlock(&gs->sl[i].s_lock); in tegra_hte_suspend_late()