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1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
26 ('3' << 8) | \
31 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)
41 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
58 # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)
64 # define V3D_INT_SPILLUSE BIT(3)
77 # define V3D_CTERR BIT(3)
98 # define V3D_RMBUSY BIT(3)
121 # define V3D_PCTRE_EN BIT(31)
139 # define PV_CONTROL_FORMAT_DSIV_18 3
152 # define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
162 # define PV_VCONTROL_DSI BIT(3)
170 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
176 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16)
182 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16)
188 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16)
204 # define PV_INT_HFP_START BIT(3)
218 #define SCALER_CHANNELS_COUNT 3
222 # define SCALER_DISPCTRL_ENABLE BIT(31)
231 /* Enables Display 0 end-of-line-N contribution to
254 # define SCALER_DISPSTAT_RESP_DECERR 3
296 # define SCALER_DISPECTRL_DSP2_MUX_SHIFT 31
297 # define SCALER_DISPECTRL_DSP2_MUX_MASK VC4_MASK(31, 31)
303 # define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
307 # define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
314 (x) * (SCALER_DISPLIST1 - \
321 (x) * (SCALER_DISPLACT1 - \
325 # define SCALER_DISPCTRLX_ENABLE BIT(31)
362 # define SCALER_DISPBKGND_AUTOHS BIT(31)
374 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
379 # define SCALER_DISPSTATX_MODE_EOF 3
387 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
390 # define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)
393 * channel. Must be 4-pixel aligned.
401 (x) * (SCALER_DISPBKGND1 - \
410 (x) * (SCALER_DISPSTAT1 - \
415 (x) * (SCALER_DISPBASE1 - \
419 (x) * (SCALER_DISPCTRL1 - \
430 # define SCALER_GAMADDR_AUTOINC BIT(31)
438 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
446 # define SCALER_OLEDOFFS_DISPFIFO_2 3
448 /* Offsets are 8-bit 2s-complement. */
487 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
542 VC4_HDMI_MAI_SAMPLE_RATE_12000 = 3,
578 /* Horizontal pack porch (htotal - hsync_end). */
581 /* Horizontal sync pulse (hsync_end - hsync_start). */
584 /* Horizontal front porch (hsync_start - hdisplay). */
594 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
602 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
606 /* Vertical sync pulse (vsync_end - vsync_start). */
609 /* Vertical front porch (vsync_start - vdisplay). */
619 /* Vertical pack porch (vtotal - vsync_end). */
624 # define VC4_HDMI_CEC_TX_EOM BIT(31)
674 # define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)
683 # define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)
713 # define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
714 # define VC4_HD_M_RAM_STANDBY (3 << 4)
728 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
734 # define VC4_HD_MAI_CTL_ENABLE BIT(3)
739 /* Single-shot reset bit. Read value is undefined. */
754 # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)
759 # define VC4_HD_VID_CTL_ENABLE BIT(31)
773 # define VC4_HD_CSC_CTL_ORDER_GRB 3
777 # define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2)
781 # define VC4_HD_CSC_CTL_MODE_CUSTOM 3
789 3
790 # define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3)
802 VC4_MASK(3, 2)
815 HVS_PIXEL_FORMAT_RGBA5551 = 3,
841 #define HVS_PIXEL_ORDER_ABGR 3
846 #define HVS_PIXEL_ORDER_XBGR 3
851 #define HVS_PIXEL_ORDER_YXCRCB 3
853 #define SCALER_CTL0_END BIT(31)
864 #define SCALER_CTL0_TILING_256B_OR_T 3
875 #define SCALER_CTL0_KEY_REPLACE 3 /* replace with value from key mask word 2 */
885 #define SCALER_CTL0_RGBA_EXPAND_ROUND 3
900 #define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3
910 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
915 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
930 #define SCALER5_POS0_VFLIP BIT(31)
933 #define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
938 #define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
966 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
971 #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3
989 * 0x2: 2, 0x3: -1}
992 #define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)
997 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
1000 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
1011 #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
1045 #define SCALER_TPZ0_VERT_RECALC BIT(31)
1056 #define SCALER_PPF_NOINTERP BIT(31)
1068 #define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1081 #define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26)
1084 /* PITCH0 fields for T-tiled. */