Lines Matching refs:VC4_SET_FIELD
167 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
169 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
171 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
174 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
176 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
178 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
181 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
183 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
185 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), in vc4_ctm_commit()
190 VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); in vc4_ctm_commit()
263 dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX); in vc4_hvs_pv_muxing_commit()
265 dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); in vc4_hvs_pv_muxing_commit()
301 VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX)); in vc5_hvs_pv_muxing_commit()
313 VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX)); in vc5_hvs_pv_muxing_commit()
325 VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX)); in vc5_hvs_pv_muxing_commit()
338 VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX)); in vc5_hvs_pv_muxing_commit()