Lines Matching +full:assigned +full:- +full:resolution +full:- +full:bits
1 // SPDX-License-Identifier: GPL-2.0-only
73 struct drm_device *dev = state->dev; in vc4_get_ctm_state()
78 ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx); in vc4_get_ctm_state()
94 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in vc4_ctm_duplicate_state()
98 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_ctm_duplicate_state()
100 return &state->base; in vc4_ctm_duplicate_state()
120 drm_atomic_private_obj_fini(&vc4->ctm_manager); in vc4_ctm_obj_fini()
127 drm_modeset_lock_init(&vc4->ctm_state_lock); in vc4_ctm_obj_init()
131 return -ENOMEM; in vc4_ctm_obj_init()
133 drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base, in vc4_ctm_obj_init()
136 return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL); in vc4_ctm_obj_init()
148 /* We have zero integer bits so we can only saturate here. */ in vc4_ctm_s31_32_to_s0_9()
151 /* Otherwise take the 9 most important fractional bits. */ in vc4_ctm_s31_32_to_s0_9()
161 struct vc4_hvs *hvs = vc4->hvs; in vc4_ctm_commit()
162 struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state); in vc4_ctm_commit()
163 struct drm_color_ctm *ctm = ctm_state->ctm; in vc4_ctm_commit()
165 if (ctm_state->fifo) { in vc4_ctm_commit()
167 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
169 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
171 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
174 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
176 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
178 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
181 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
183 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
185 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), in vc4_ctm_commit()
190 VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); in vc4_ctm_commit()
196 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_hvs_get_new_global_state()
199 priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels); in vc4_hvs_get_new_global_state()
201 return ERR_PTR(-EINVAL); in vc4_hvs_get_new_global_state()
209 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_hvs_get_old_global_state()
212 priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels); in vc4_hvs_get_old_global_state()
214 return ERR_PTR(-EINVAL); in vc4_hvs_get_old_global_state()
222 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_hvs_get_global_state()
225 priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels); in vc4_hvs_get_global_state()
235 struct vc4_hvs *hvs = vc4->hvs; in vc4_hvs_pv_muxing_commit()
246 if (!crtc_state->active) in vc4_hvs_pv_muxing_commit()
249 if (vc4_state->assigned_channel != 2) in vc4_hvs_pv_muxing_commit()
259 * TXP IP, and we need to disable the FIFO2 -> pixelvalve1 in vc4_hvs_pv_muxing_commit()
262 if (vc4_crtc->feeds_txp) in vc4_hvs_pv_muxing_commit()
276 struct vc4_hvs *hvs = vc4->hvs; in vc5_hvs_pv_muxing_commit()
286 unsigned int channel = vc4_state->assigned_channel; in vc5_hvs_pv_muxing_commit()
288 if (!vc4_state->update_muxing) in vc5_hvs_pv_muxing_commit()
291 switch (vc4_crtc->data->hvs_output) { in vc5_hvs_pv_muxing_commit()
293 drm_WARN_ON(&vc4->base, in vc5_hvs_pv_muxing_commit()
349 struct drm_device *dev = state->dev; in vc4_atomic_commit_tail()
351 struct vc4_hvs *hvs = vc4->hvs; in vc4_atomic_commit_tail()
370 if (!new_crtc_state->commit) in vc4_atomic_commit_tail()
374 vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel); in vc4_atomic_commit_tail()
381 if (!old_hvs_state->fifo_state[channel].in_use) in vc4_atomic_commit_tail()
384 commit = old_hvs_state->fifo_state[channel].pending_commit; in vc4_atomic_commit_tail()
393 old_hvs_state->fifo_state[channel].pending_commit = NULL; in vc4_atomic_commit_tail()
396 if (vc4->is_vc5) { in vc4_atomic_commit_tail()
397 unsigned long state_rate = max(old_hvs_state->core_clock_rate, in vc4_atomic_commit_tail()
398 new_hvs_state->core_clock_rate); in vc4_atomic_commit_tail()
408 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
415 if (vc4->is_vc5) in vc4_atomic_commit_tail()
433 if (vc4->is_vc5) { in vc4_atomic_commit_tail()
435 new_hvs_state->core_clock_rate); in vc4_atomic_commit_tail()
441 WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate)); in vc4_atomic_commit_tail()
444 clk_get_rate(hvs->core_clk)); in vc4_atomic_commit_tail()
463 vc4_crtc_state->assigned_channel; in vc4_atomic_commit_setup()
468 if (!hvs_state->fifo_state[channel].in_use) in vc4_atomic_commit_setup()
471 hvs_state->fifo_state[channel].pending_commit = in vc4_atomic_commit_setup()
472 drm_crtc_commit_get(crtc_state->commit); in vc4_atomic_commit_setup()
485 if (WARN_ON_ONCE(vc4->is_vc5)) in vc4_fb_create()
486 return ERR_PTR(-ENODEV); in vc4_fb_create()
491 if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) { in vc4_fb_create()
496 mode_cmd->handles[0]); in vc4_fb_create()
499 mode_cmd->handles[0]); in vc4_fb_create()
500 return ERR_PTR(-ENOENT); in vc4_fb_create()
506 if (bo->t_format) { in vc4_fb_create()
537 if (!new_crtc_state->ctm && old_crtc_state->ctm) { in vc4_ctm_atomic_check()
538 ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); in vc4_ctm_atomic_check()
541 ctm_state->fifo = 0; in vc4_ctm_atomic_check()
546 if (new_crtc_state->ctm == old_crtc_state->ctm) in vc4_ctm_atomic_check()
550 ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); in vc4_ctm_atomic_check()
556 if (new_crtc_state->ctm) { in vc4_ctm_atomic_check()
560 /* fifo is 1-based since 0 disables CTM. */ in vc4_ctm_atomic_check()
561 int fifo = vc4_crtc_state->assigned_channel + 1; in vc4_ctm_atomic_check()
566 if (ctm_state->fifo && ctm_state->fifo != fifo) { in vc4_ctm_atomic_check()
568 return -EINVAL; in vc4_ctm_atomic_check()
573 * no integer bits. in vc4_ctm_atomic_check()
575 ctm = new_crtc_state->ctm->data; in vc4_ctm_atomic_check()
576 for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) { in vc4_ctm_atomic_check()
577 u64 val = ctm->matrix[i]; in vc4_ctm_atomic_check()
581 return -EINVAL; in vc4_ctm_atomic_check()
584 ctm_state->fifo = fifo; in vc4_ctm_atomic_check()
585 ctm_state->ctm = ctm; in vc4_ctm_atomic_check()
595 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_load_tracker_atomic_check()
602 &vc4->load_tracker); in vc4_load_tracker_atomic_check()
611 if (old_plane_state->fb && old_plane_state->crtc) { in vc4_load_tracker_atomic_check()
613 load_state->membus_load -= vc4_plane_state->membus_load; in vc4_load_tracker_atomic_check()
614 load_state->hvs_load -= vc4_plane_state->hvs_load; in vc4_load_tracker_atomic_check()
617 if (new_plane_state->fb && new_plane_state->crtc) { in vc4_load_tracker_atomic_check()
619 load_state->membus_load += vc4_plane_state->membus_load; in vc4_load_tracker_atomic_check()
620 load_state->hvs_load += vc4_plane_state->hvs_load; in vc4_load_tracker_atomic_check()
625 if (!vc4->load_tracker_enabled) in vc4_load_tracker_atomic_check()
631 if (load_state->membus_load > SZ_1G + SZ_512M) in vc4_load_tracker_atomic_check()
632 return -ENOSPC; in vc4_load_tracker_atomic_check()
637 if (load_state->hvs_load > 240000000ULL) in vc4_load_tracker_atomic_check()
638 return -ENOSPC; in vc4_load_tracker_atomic_check()
648 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in vc4_load_tracker_duplicate_state()
652 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_load_tracker_duplicate_state()
654 return &state->base; in vc4_load_tracker_duplicate_state()
675 drm_atomic_private_obj_fini(&vc4->load_tracker); in vc4_load_tracker_obj_fini()
684 return -ENOMEM; in vc4_load_tracker_obj_init()
686 drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker, in vc4_load_tracker_obj_init()
687 &load_state->base, in vc4_load_tracker_obj_init()
690 return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL); in vc4_load_tracker_obj_init()
696 struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state); in vc4_hvs_channels_duplicate_state()
704 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_hvs_channels_duplicate_state()
707 state->fifo_state[i].in_use = old_state->fifo_state[i].in_use; in vc4_hvs_channels_duplicate_state()
708 state->fifo_state[i].fifo_load = old_state->fifo_state[i].fifo_load; in vc4_hvs_channels_duplicate_state()
711 state->core_clock_rate = old_state->core_clock_rate; in vc4_hvs_channels_duplicate_state()
713 return &state->base; in vc4_hvs_channels_duplicate_state()
723 if (!hvs_state->fifo_state[i].pending_commit) in vc4_hvs_channels_destroy_state()
726 drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit); in vc4_hvs_channels_destroy_state()
739 drm_printf(p, "\tCore Clock Rate: %lu\n", hvs_state->core_clock_rate); in vc4_hvs_channels_print_state()
743 drm_printf(p, "\t\tin use=%d\n", hvs_state->fifo_state[i].in_use); in vc4_hvs_channels_print_state()
744 drm_printf(p, "\t\tload=%lu\n", hvs_state->fifo_state[i].fifo_load); in vc4_hvs_channels_print_state()
758 drm_atomic_private_obj_fini(&vc4->hvs_channels); in vc4_hvs_channels_obj_fini()
767 return -ENOMEM; in vc4_hvs_channels_obj_init()
769 drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels, in vc4_hvs_channels_obj_init()
770 &state->base, in vc4_hvs_channels_obj_init()
773 return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL); in vc4_hvs_channels_obj_init()
785 * - When running in a dual-display setup (so with two CRTCs involved),
792 * - To fix the above, we can't use drm_atomic_get_crtc_state on all
798 * doing a modetest -v first on HDMI1 and then on HDMI0.
800 * - Since we need the pixelvalve to be disabled and enabled back when
801 * the FIFO is changed, we should keep the FIFO assigned for as long
804 * single display, and changing the resolution down and then back up.
819 for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++) in vc4_pv_muxing_atomic_check()
820 if (!hvs_new_state->fifo_state[i].in_use) in vc4_pv_muxing_atomic_check()
832 drm_dbg(dev, "%s: Trying to find a channel.\n", crtc->name); in vc4_pv_muxing_atomic_check()
835 if (old_crtc_state->enable == new_crtc_state->enable) { in vc4_pv_muxing_atomic_check()
836 if (new_crtc_state->enable) in vc4_pv_muxing_atomic_check()
838 crtc->name, new_vc4_crtc_state->assigned_channel); in vc4_pv_muxing_atomic_check()
840 drm_dbg(dev, "%s: Disabled, ignoring.\n", crtc->name); in vc4_pv_muxing_atomic_check()
846 new_vc4_crtc_state->update_muxing = true; in vc4_pv_muxing_atomic_check()
849 if (!new_crtc_state->enable) { in vc4_pv_muxing_atomic_check()
850 channel = old_vc4_crtc_state->assigned_channel; in vc4_pv_muxing_atomic_check()
853 crtc->name, channel); in vc4_pv_muxing_atomic_check()
855 hvs_new_state->fifo_state[channel].in_use = false; in vc4_pv_muxing_atomic_check()
856 new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; in vc4_pv_muxing_atomic_check()
877 * earlier CRTC that had multiple routes is assigned in vc4_pv_muxing_atomic_check()
884 matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels; in vc4_pv_muxing_atomic_check()
886 return -EINVAL; in vc4_pv_muxing_atomic_check()
888 channel = ffs(matching_channels) - 1; in vc4_pv_muxing_atomic_check()
890 drm_dbg(dev, "Assigned HVS channel %d to CRTC %s\n", channel, crtc->name); in vc4_pv_muxing_atomic_check()
891 new_vc4_crtc_state->assigned_channel = channel; in vc4_pv_muxing_atomic_check()
893 hvs_new_state->fifo_state[channel].in_use = true; in vc4_pv_muxing_atomic_check()
902 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_core_clock_atomic_check()
914 &vc4->load_tracker); in vc4_core_clock_atomic_check()
928 if (old_crtc_state->active) { in vc4_core_clock_atomic_check()
931 unsigned int channel = old_vc4_state->assigned_channel; in vc4_core_clock_atomic_check()
933 hvs_new_state->fifo_state[channel].fifo_load = 0; in vc4_core_clock_atomic_check()
936 if (new_crtc_state->active) { in vc4_core_clock_atomic_check()
939 unsigned int channel = new_vc4_state->assigned_channel; in vc4_core_clock_atomic_check()
941 hvs_new_state->fifo_state[channel].fifo_load = in vc4_core_clock_atomic_check()
942 new_vc4_state->hvs_load; in vc4_core_clock_atomic_check()
949 if (!hvs_new_state->fifo_state[i].in_use) in vc4_core_clock_atomic_check()
954 hvs_new_state->fifo_state[i].fifo_load, in vc4_core_clock_atomic_check()
958 pixel_rate = load_state->hvs_load; in vc4_core_clock_atomic_check()
965 hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate); in vc4_core_clock_atomic_check()
1022 if (!vc4->is_vc5) { in vc4_kms_load()
1026 vc4->load_tracker_enabled = true; in vc4_kms_load()
1030 dev->vblank_disable_immediate = true; in vc4_kms_load()
1032 ret = drm_vblank_init(dev, dev->mode_config.num_crtc); in vc4_kms_load()
1034 dev_err(dev->dev, "failed to initialize vblank\n"); in vc4_kms_load()
1038 if (vc4->is_vc5) { in vc4_kms_load()
1039 dev->mode_config.max_width = 7680; in vc4_kms_load()
1040 dev->mode_config.max_height = 7680; in vc4_kms_load()
1042 dev->mode_config.max_width = 2048; in vc4_kms_load()
1043 dev->mode_config.max_height = 2048; in vc4_kms_load()
1046 dev->mode_config.funcs = vc4->is_vc5 ? &vc5_mode_funcs : &vc4_mode_funcs; in vc4_kms_load()
1047 dev->mode_config.helper_private = &vc4_mode_config_helpers; in vc4_kms_load()
1048 dev->mode_config.preferred_depth = 24; in vc4_kms_load()
1049 dev->mode_config.async_page_flip = true; in vc4_kms_load()