18 #define VC4_HDMI_TX_PHY_RESET_CTL_TX_0_RESET	BIT(0)
36 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_SHIFT	0
37 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK	VC4_MASK(4, 0)
45 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_SHIFT		0
46 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_MASK		VC4_MASK(4, 0)
56 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_SHIFT	0
57 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_MASK	VC4_MASK(3, 0)
69 #define VC4_HDMI_TX_PHY_CTL_3_ICP_SHIFT			0
70 #define VC4_HDMI_TX_PHY_CTL_3_ICP_MASK			VC4_MASK(5, 0)
94 #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_SHIFT		0
95 #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_MASK		VC4_MASK(3, 0)
103 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_MASK	VC4_MASK(1, 0)
104 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_SHIFT	0
106 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_MASK		VC4_MASK(27, 0)
107 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_SHIFT	0
109 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_MASK		VC4_MASK(27, 0)
110 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_SHIFT	0
114 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_MASK	VC4_MASK(15, 0)
115 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_SHIFT	0
122 #define VC4_HDMI_RM_OFFSET_OFFSET_SHIFT			0
123 #define VC4_HDMI_RM_OFFSET_OFFSET_MASK			VC4_MASK(30, 0)
141 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);  in vc4_hdmi_phy_init()
142 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);  in vc4_hdmi_phy_init()
152 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);  in vc4_hdmi_phy_disable()
182 	unsigned int _vco_div = 0;  in phy_get_vco_freq()
183 	unsigned int _vco_sel = 0;  in phy_get_vco_freq()
202 		return 0x1c;  in phy_get_cp_current()
204 	return 0x18;  in phy_get_cp_current()
210 	u64 offset = 0;  in phy_get_rm_offset()
224 		return 0xf;  in phy_get_vco_gain()
227 		return 0xc;  in phy_get_vco_gain()
230 		return 0x6;  in phy_get_vco_gain()
233 		return 0x5;  in phy_get_vco_gain()
236 		return 0x7;  in phy_get_vco_gain()
238 	return 0x2;  in phy_get_vco_gain()
260 		0, 50000000,
262 			{{0x0, 0x0A}, 0x12, 0x0},
263 			{{0x0, 0x0A}, 0x12, 0x0},
264 			{{0x0, 0x0A}, 0x12, 0x0}
266 		{{0x0, 0x0A}, 0x18, 0x0},
271 			{{0x0, 0x09}, 0x12, 0x0},
272 			{{0x0, 0x09}, 0x12, 0x0},
273 			{{0x0, 0x09}, 0x12, 0x0}
275 		{{0x0, 0x0C}, 0x18, 0x3},
280 			{{0x0, 0x09}, 0x12, 0x0},
281 			{{0x0, 0x09}, 0x12, 0x0},
282 			{{0x0, 0x09}, 0x12, 0x0}
284 		{{0x0, 0x0C}, 0x18, 0x3},
289 			{{0x0, 0x0F}, 0x12, 0x1},
290 			{{0x0, 0x0F}, 0x12, 0x1},
291 			{{0x0, 0x0F}, 0x12, 0x1}
293 		{{0x0, 0x0C}, 0x18, 0x3},
298 			{{0x2, 0x0D}, 0x12, 0x1},
299 			{{0x2, 0x0D}, 0x12, 0x1},
300 			{{0x2, 0x0D}, 0x12, 0x1}
302 		{{0x0, 0x0C}, 0x18, 0xF},
307 			{{0x0, 0x1B}, 0x12, 0xF},
308 			{{0x0, 0x1B}, 0x12, 0xF},
309 			{{0x0, 0x1B}, 0x12, 0xF}
311 		{{0x0, 0x0A}, 0x12, 0xF},
316 			{{0x0, 0x1C}, 0x12, 0xF},
317 			{{0x0, 0x1C}, 0x12, 0xF},
318 			{{0x0, 0x1C}, 0x12, 0xF}
320 		{{0x0, 0x0B}, 0x13, 0xF},
329 	for (i = 0; i < count; i++) {  in phy_get_settings()
359 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0x0f);  in vc5_hdmi_reset_phy()
399 		   VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT));  in vc5_hdmi_phy_init()
404 		   VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT));  in vc5_hdmi_phy_init()
415 		   VC4_SET_FIELD(0xe147, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD) |  in vc5_hdmi_phy_init()
416 		   VC4_SET_FIELD(0xe14, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD));  in vc5_hdmi_phy_init()
429 		   VC4_SET_FIELD(0x8a, VC4_HDMI_TX_PHY_PLL_CTL_1_CPP));  in vc5_hdmi_phy_init()
442 		word_sel = 0;  in vc5_hdmi_phy_init()