Lines Matching refs:pixel_rep
1226 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; in vc4_hdmi_set_timings() local
1252 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc4_hdmi_set_timings()
1257 mode->hsync_end) * pixel_rep, in vc4_hdmi_set_timings()
1260 mode->hsync_start) * pixel_rep, in vc4_hdmi_set_timings()
1263 mode->hdisplay) * pixel_rep, in vc4_hdmi_set_timings()
1274 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); in vc4_hdmi_set_timings()
1292 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; in vc5_hdmi_set_timings() local
1298 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), in vc5_hdmi_set_timings()
1320 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc5_hdmi_set_timings()
1323 mode->hdisplay) * pixel_rep, in vc5_hdmi_set_timings()
1328 mode->hsync_end) * pixel_rep, in vc5_hdmi_set_timings()
1331 mode->hsync_start) * pixel_rep, in vc5_hdmi_set_timings()
1384 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); in vc5_hdmi_set_timings()