Lines Matching full:dsi
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
550 /* General DSI hardware state. */
571 /* DSI channel for the panel we're connected to. */
578 /* Input clock from CPRMAN to the digital PHY, for the DSI
583 /* Input clock to the analog PHY, used to generate the DSI bit
588 /* HS Clocks generated within the DSI analog PHY. */
613 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val) in dsi_dma_workaround_write() argument
615 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
622 writel(val, dsi->regs + offset); in dsi_dma_workaround_write()
626 *dsi->reg_dma_mem = val; in dsi_dma_workaround_write()
629 dsi->reg_paddr + offset, in dsi_dma_workaround_write()
630 dsi->reg_dma_paddr, in dsi_dma_workaround_write()
648 #define DSI_READ(offset) readl(dsi->regs + (offset))
649 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
651 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
653 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
654 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
706 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch) in vc4_dsi_latch_ulps() argument
719 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps) in vc4_dsi_ulps() argument
721 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; in vc4_dsi_ulps()
724 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
725 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
726 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
729 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
730 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
731 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
734 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
735 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
736 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
748 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
749 "Timeout waiting for DSI ULPS entry: STAT 0x%08x", in vc4_dsi_ulps()
752 vc4_dsi_latch_ulps(dsi, false); in vc4_dsi_ulps()
756 /* The DSI module can't be disabled while the module is in vc4_dsi_ulps()
761 vc4_dsi_latch_ulps(dsi, ulps); in vc4_dsi_ulps()
767 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
768 "Timeout waiting for DSI STOP entry: STAT 0x%08x", in vc4_dsi_ulps()
795 struct vc4_dsi *dsi = to_vc4_dsi(encoder); in vc4_dsi_encoder_disable() local
796 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_disable()
799 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_disable()
803 if (iter == dsi->bridge) in vc4_dsi_encoder_disable()
807 vc4_dsi_ulps(dsi, true); in vc4_dsi_encoder_disable()
809 list_for_each_entry_from(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_disable()
814 clk_disable_unprepare(dsi->pll_phy_clock); in vc4_dsi_encoder_disable()
815 clk_disable_unprepare(dsi->escape_clock); in vc4_dsi_encoder_disable()
816 clk_disable_unprepare(dsi->pixel_clock); in vc4_dsi_encoder_disable()
822 * DSI PLL divider.
826 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
827 * the pixel clock), only has an integer divider off of DSI.
838 struct vc4_dsi *dsi = to_vc4_dsi(encoder); in vc4_dsi_encoder_mode_fixup() local
839 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); in vc4_dsi_encoder_mode_fixup()
842 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_encoder_mode_fixup()
857 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_encoder_mode_fixup()
873 struct vc4_dsi *dsi = to_vc4_dsi(encoder); in vc4_dsi_encoder_enable() local
874 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_enable()
888 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port); in vc4_dsi_encoder_enable()
893 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_encoder_enable()
894 dev_info(&dsi->pdev->dev, "DSI regs before:\n"); in vc4_dsi_encoder_enable()
895 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_encoder_enable()
902 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; in vc4_dsi_encoder_enable()
903 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); in vc4_dsi_encoder_enable()
905 dev_err(&dsi->pdev->dev, in vc4_dsi_encoder_enable()
909 /* Reset the DSI and all its fifos. */ in vc4_dsi_encoder_enable()
922 if (dsi->variant->port == 0) { in vc4_dsi_encoder_enable()
926 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
929 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in vc4_dsi_encoder_enable()
950 if (dsi->lanes < 4) in vc4_dsi_encoder_enable()
952 if (dsi->lanes < 3) in vc4_dsi_encoder_enable()
954 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
967 ret = clk_prepare_enable(dsi->escape_clock); in vc4_dsi_encoder_enable()
969 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret); in vc4_dsi_encoder_enable()
973 ret = clk_prepare_enable(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
975 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret); in vc4_dsi_encoder_enable()
979 hs_clock = clk_get_rate(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
986 * pixel clock for pushing pixels into DSI. in vc4_dsi_encoder_enable()
989 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); in vc4_dsi_encoder_enable()
995 ret = clk_prepare_enable(dsi->pixel_clock); in vc4_dsi_encoder_enable()
997 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret); in vc4_dsi_encoder_enable()
1001 /* How many ns one DSI unit interval is. Note that the clock in vc4_dsi_encoder_enable()
1065 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | in vc4_dsi_encoder_enable()
1066 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | in vc4_dsi_encoder_enable()
1067 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | in vc4_dsi_encoder_enable()
1069 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? in vc4_dsi_encoder_enable()
1071 (dsi->variant->port == 0 ? in vc4_dsi_encoder_enable()
1097 if (dsi->variant->port == 0) in vc4_dsi_encoder_enable()
1107 vc4_dsi_ulps(dsi, false); in vc4_dsi_encoder_enable()
1109 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_enable()
1114 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in vc4_dsi_encoder_enable()
1116 VC4_SET_FIELD(dsi->divider, in vc4_dsi_encoder_enable()
1118 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_encoder_enable()
1129 list_for_each_entry(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_enable()
1135 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_encoder_enable()
1136 dev_info(&dsi->pdev->dev, "DSI regs after:\n"); in vc4_dsi_encoder_enable()
1137 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_encoder_enable()
1144 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_transfer() local
1222 dsi->xfer_result = 0; in vc4_dsi_host_transfer()
1223 reinit_completion(&dsi->xfer_completion); in vc4_dsi_host_transfer()
1224 if (dsi->variant->port == 0) { in vc4_dsi_host_transfer()
1252 if (!wait_for_completion_timeout(&dsi->xfer_completion, in vc4_dsi_host_transfer()
1254 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); in vc4_dsi_host_transfer()
1255 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", in vc4_dsi_host_transfer()
1259 ret = dsi->xfer_result; in vc4_dsi_host_transfer()
1276 DRM_ERROR("DSI returned %db, expecting %db\n", in vc4_dsi_host_transfer()
1299 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret); in vc4_dsi_host_transfer()
1316 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_attach() local
1318 dsi->lanes = device->lanes; in vc4_dsi_host_attach()
1319 dsi->channel = device->channel; in vc4_dsi_host_attach()
1320 dsi->mode_flags = device->mode_flags; in vc4_dsi_host_attach()
1324 dsi->format = DSI_PFORMAT_RGB888; in vc4_dsi_host_attach()
1325 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1328 dsi->format = DSI_PFORMAT_RGB666; in vc4_dsi_host_attach()
1329 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1332 dsi->format = DSI_PFORMAT_RGB666_PACKED; in vc4_dsi_host_attach()
1333 dsi->divider = 18 / dsi->lanes; in vc4_dsi_host_attach()
1336 dsi->format = DSI_PFORMAT_RGB565; in vc4_dsi_host_attach()
1337 dsi->divider = 16 / dsi->lanes; in vc4_dsi_host_attach()
1340 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", in vc4_dsi_host_attach()
1341 dsi->format); in vc4_dsi_host_attach()
1345 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { in vc4_dsi_host_attach()
1346 dev_err(&dsi->pdev->dev, in vc4_dsi_host_attach()
1351 return component_add(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_attach()
1357 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_detach() local
1359 component_del(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_detach()
1378 struct vc4_dsi *dsi = to_vc4_dsi(encoder); in vc4_dsi_late_register() local
1381 ret = vc4_debugfs_add_regset32(drm->primary, dsi->variant->debugfs_name, in vc4_dsi_late_register()
1382 &dsi->regset); in vc4_dsi_late_register()
1422 static void dsi_handle_error(struct vc4_dsi *dsi, in dsi_handle_error() argument
1429 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type); in dsi_handle_error()
1441 struct vc4_dsi *dsi = data; in vc4_dsi_irq_defer_to_thread_handler() local
1456 struct vc4_dsi *dsi = data; in vc4_dsi_irq_handler() local
1462 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1464 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1466 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1468 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1470 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1472 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1474 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1476 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1479 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE : in vc4_dsi_irq_handler()
1482 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1485 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1486 dsi->xfer_result = -ETIMEDOUT; in vc4_dsi_irq_handler()
1496 * @dsi: DSI encoder
1499 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi) in vc4_dsi_init_phy_clocks() argument
1501 struct device *dev = &dsi->pdev->dev; in vc4_dsi_init_phy_clocks()
1502 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); in vc4_dsi_init_phy_clocks()
1513 dsi->clk_onecell = devm_kzalloc(dev, in vc4_dsi_init_phy_clocks()
1514 sizeof(*dsi->clk_onecell) + in vc4_dsi_init_phy_clocks()
1518 if (!dsi->clk_onecell) in vc4_dsi_init_phy_clocks()
1520 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); in vc4_dsi_init_phy_clocks()
1523 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; in vc4_dsi_init_phy_clocks()
1529 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name); in vc4_dsi_init_phy_clocks()
1536 * setting both our parent DSI PLL's rate and this in vc4_dsi_init_phy_clocks()
1554 dsi->clk_onecell->hws[i] = &fix->hw; in vc4_dsi_init_phy_clocks()
1559 dsi->clk_onecell); in vc4_dsi_init_phy_clocks()
1564 struct vc4_dsi *dsi = ptr; in vc4_dsi_dma_mem_release() local
1565 struct device *dev = &dsi->pdev->dev; in vc4_dsi_dma_mem_release()
1567 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr); in vc4_dsi_dma_mem_release()
1568 dsi->reg_dma_mem = NULL; in vc4_dsi_dma_mem_release()
1573 struct vc4_dsi *dsi = ptr; in vc4_dsi_dma_chan_release() local
1575 dma_release_channel(dsi->reg_dma_chan); in vc4_dsi_dma_chan_release()
1576 dsi->reg_dma_chan = NULL; in vc4_dsi_dma_chan_release()
1581 struct vc4_dsi *dsi = in vc4_dsi_release() local
1584 kfree(dsi); in vc4_dsi_release()
1587 static void vc4_dsi_get(struct vc4_dsi *dsi) in vc4_dsi_get() argument
1589 kref_get(&dsi->kref); in vc4_dsi_get()
1592 static void vc4_dsi_put(struct vc4_dsi *dsi) in vc4_dsi_put() argument
1594 kref_put(&dsi->kref, &vc4_dsi_release); in vc4_dsi_put()
1599 struct vc4_dsi *dsi = ptr; in vc4_dsi_release_action() local
1601 vc4_dsi_put(dsi); in vc4_dsi_release_action()
1608 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_bind() local
1609 struct drm_encoder *encoder = &dsi->encoder.base; in vc4_dsi_bind()
1612 vc4_dsi_get(dsi); in vc4_dsi_bind()
1614 ret = drmm_add_action_or_reset(drm, vc4_dsi_release_action, dsi); in vc4_dsi_bind()
1618 dsi->variant = of_device_get_match_data(dev); in vc4_dsi_bind()
1620 INIT_LIST_HEAD(&dsi->bridge_chain); in vc4_dsi_bind()
1621 dsi->encoder.type = dsi->variant->port ? in vc4_dsi_bind()
1624 dsi->regs = vc4_ioremap_regs(pdev, 0); in vc4_dsi_bind()
1625 if (IS_ERR(dsi->regs)) in vc4_dsi_bind()
1626 return PTR_ERR(dsi->regs); in vc4_dsi_bind()
1628 dsi->regset.base = dsi->regs; in vc4_dsi_bind()
1629 dsi->regset.regs = dsi->variant->regs; in vc4_dsi_bind()
1630 dsi->regset.nregs = dsi->variant->nregs; in vc4_dsi_bind()
1642 if (dsi->variant->broken_axi_workaround) { in vc4_dsi_bind()
1645 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, in vc4_dsi_bind()
1646 &dsi->reg_dma_paddr, in vc4_dsi_bind()
1648 if (!dsi->reg_dma_mem) { in vc4_dsi_bind()
1653 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_mem_release, dsi); in vc4_dsi_bind()
1660 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); in vc4_dsi_bind()
1661 if (IS_ERR(dsi->reg_dma_chan)) { in vc4_dsi_bind()
1662 ret = PTR_ERR(dsi->reg_dma_chan); in vc4_dsi_bind()
1669 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_chan_release, dsi); in vc4_dsi_bind()
1677 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, in vc4_dsi_bind()
1681 init_completion(&dsi->xfer_completion); in vc4_dsi_bind()
1687 if (dsi->reg_dma_mem) in vc4_dsi_bind()
1692 "vc4 dsi", dsi); in vc4_dsi_bind()
1695 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); in vc4_dsi_bind()
1702 dsi->escape_clock = devm_clk_get(dev, "escape"); in vc4_dsi_bind()
1703 if (IS_ERR(dsi->escape_clock)) { in vc4_dsi_bind()
1704 ret = PTR_ERR(dsi->escape_clock); in vc4_dsi_bind()
1710 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); in vc4_dsi_bind()
1711 if (IS_ERR(dsi->pll_phy_clock)) { in vc4_dsi_bind()
1712 ret = PTR_ERR(dsi->pll_phy_clock); in vc4_dsi_bind()
1718 dsi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dsi_bind()
1719 if (IS_ERR(dsi->pixel_clock)) { in vc4_dsi_bind()
1720 ret = PTR_ERR(dsi->pixel_clock); in vc4_dsi_bind()
1726 dsi->bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0); in vc4_dsi_bind()
1727 if (IS_ERR(dsi->bridge)) in vc4_dsi_bind()
1728 return PTR_ERR(dsi->bridge); in vc4_dsi_bind()
1731 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); in vc4_dsi_bind()
1737 ret = vc4_dsi_init_phy_clocks(dsi); in vc4_dsi_bind()
1754 ret = drm_bridge_attach(encoder, dsi->bridge, NULL, 0); in vc4_dsi_bind()
1762 list_splice_init(&encoder->bridge_chain, &dsi->bridge_chain); in vc4_dsi_bind()
1770 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_unbind() local
1771 struct drm_encoder *encoder = &dsi->encoder.base; in vc4_dsi_unbind()
1777 list_splice_init(&dsi->bridge_chain, &encoder->bridge_chain); in vc4_dsi_unbind()
1788 struct vc4_dsi *dsi; in vc4_dsi_dev_probe() local
1790 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL); in vc4_dsi_dev_probe()
1791 if (!dsi) in vc4_dsi_dev_probe()
1793 dev_set_drvdata(dev, dsi); in vc4_dsi_dev_probe()
1795 kref_init(&dsi->kref); in vc4_dsi_dev_probe()
1796 dsi->pdev = pdev; in vc4_dsi_dev_probe()
1797 dsi->dsi_host.ops = &vc4_dsi_host_ops; in vc4_dsi_dev_probe()
1798 dsi->dsi_host.dev = dev; in vc4_dsi_dev_probe()
1799 mipi_dsi_host_register(&dsi->dsi_host); in vc4_dsi_dev_probe()
1807 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_dev_remove() local
1809 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_remove()
1810 vc4_dsi_put(dsi); in vc4_dsi_dev_remove()