Lines Matching +full:bcm2835 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0-only
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/i2c.h>
146 * of going to LP-STOP.
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
539 /* Whether we're on bcm2835's DSI0 or DSI1. */
615 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
622 writel(val, dsi->regs + offset); in dsi_dma_workaround_write()
626 *dsi->reg_dma_mem = val; in dsi_dma_workaround_write()
628 tx = chan->device->device_prep_dma_memcpy(chan, in dsi_dma_workaround_write()
629 dsi->reg_paddr + offset, in dsi_dma_workaround_write()
630 dsi->reg_dma_paddr, in dsi_dma_workaround_write()
637 cookie = tx->tx_submit(tx); in dsi_dma_workaround_write()
648 #define DSI_READ(offset) readl(dsi->regs + (offset))
651 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
653 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
654 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
721 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; in vc4_dsi_ulps()
724 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
725 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
726 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
729 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
730 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
731 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
734 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
735 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
736 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
748 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
767 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
796 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_disable()
799 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_disable()
800 if (iter->funcs->disable) in vc4_dsi_encoder_disable()
801 iter->funcs->disable(iter); in vc4_dsi_encoder_disable()
803 if (iter == dsi->bridge) in vc4_dsi_encoder_disable()
809 list_for_each_entry_from(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_disable()
810 if (iter->funcs->post_disable) in vc4_dsi_encoder_disable()
811 iter->funcs->post_disable(iter); in vc4_dsi_encoder_disable()
814 clk_disable_unprepare(dsi->pll_phy_clock); in vc4_dsi_encoder_disable()
815 clk_disable_unprepare(dsi->escape_clock); in vc4_dsi_encoder_disable()
816 clk_disable_unprepare(dsi->pixel_clock); in vc4_dsi_encoder_disable()
821 /* Extends the mode's blank intervals to handle BCM2835's integer-only
831 * higher-than-expected clock rate to the panel, but that's what the
839 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); in vc4_dsi_encoder_mode_fixup()
841 unsigned long pixel_clock_hz = mode->clock * 1000; in vc4_dsi_encoder_mode_fixup()
842 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_encoder_mode_fixup()
857 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_encoder_mode_fixup()
859 adjusted_mode->clock = pixel_clock_hz / 1000; in vc4_dsi_encoder_mode_fixup()
862 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / in vc4_dsi_encoder_mode_fixup()
863 mode->clock; in vc4_dsi_encoder_mode_fixup()
864 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal; in vc4_dsi_encoder_mode_fixup()
865 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal; in vc4_dsi_encoder_mode_fixup()
872 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; in vc4_dsi_encoder_enable()
874 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_enable()
881 unsigned long pixel_clock_hz = mode->clock * 1000; in vc4_dsi_encoder_enable()
888 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port); in vc4_dsi_encoder_enable()
893 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_encoder_enable()
894 dev_info(&dsi->pdev->dev, "DSI regs before:\n"); in vc4_dsi_encoder_enable()
895 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_encoder_enable()
902 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; in vc4_dsi_encoder_enable()
903 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); in vc4_dsi_encoder_enable()
905 dev_err(&dsi->pdev->dev, in vc4_dsi_encoder_enable()
922 if (dsi->variant->port == 0) { in vc4_dsi_encoder_enable()
926 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
929 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in vc4_dsi_encoder_enable()
950 if (dsi->lanes < 4) in vc4_dsi_encoder_enable()
952 if (dsi->lanes < 3) in vc4_dsi_encoder_enable()
954 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
967 ret = clk_prepare_enable(dsi->escape_clock); in vc4_dsi_encoder_enable()
973 ret = clk_prepare_enable(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
979 hs_clock = clk_get_rate(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
989 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); in vc4_dsi_encoder_enable()
995 ret = clk_prepare_enable(dsi->pixel_clock); in vc4_dsi_encoder_enable()
1040 /* T_INIT is how long STOP is driven after power-up to in vc4_dsi_encoder_enable()
1041 * indicate to the slave (also coming out of power-up) that in vc4_dsi_encoder_enable()
1044 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and in vc4_dsi_encoder_enable()
1065 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | in vc4_dsi_encoder_enable()
1066 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | in vc4_dsi_encoder_enable()
1067 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | in vc4_dsi_encoder_enable()
1069 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? in vc4_dsi_encoder_enable()
1071 (dsi->variant->port == 0 ? in vc4_dsi_encoder_enable()
1072 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : in vc4_dsi_encoder_enable()
1073 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT))); in vc4_dsi_encoder_enable()
1097 if (dsi->variant->port == 0) in vc4_dsi_encoder_enable()
1109 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_enable()
1110 if (iter->funcs->pre_enable) in vc4_dsi_encoder_enable()
1111 iter->funcs->pre_enable(iter); in vc4_dsi_encoder_enable()
1114 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in vc4_dsi_encoder_enable()
1116 VC4_SET_FIELD(dsi->divider, in vc4_dsi_encoder_enable()
1118 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_encoder_enable()
1129 list_for_each_entry(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_enable()
1130 if (iter->funcs->enable) in vc4_dsi_encoder_enable()
1131 iter->funcs->enable(iter); in vc4_dsi_encoder_enable()
1135 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_encoder_enable()
1136 dev_info(&dsi->pdev->dev, "DSI regs after:\n"); in vc4_dsi_encoder_enable()
1137 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_encoder_enable()
1148 bool is_long = mipi_dsi_packet_format_is_long(msg->type); in vc4_dsi_host_transfer()
1159 * The command FIFO takes byte-oriented data, but is of in vc4_dsi_host_transfer()
1173 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) / in vc4_dsi_host_transfer()
1182 if (msg->rx_len) { in vc4_dsi_host_transfer()
1202 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in vc4_dsi_host_transfer()
1222 dsi->xfer_result = 0; in vc4_dsi_host_transfer()
1223 reinit_completion(&dsi->xfer_completion); in vc4_dsi_host_transfer()
1224 if (dsi->variant->port == 0) { in vc4_dsi_host_transfer()
1227 if (msg->rx_len) { in vc4_dsi_host_transfer()
1239 if (msg->rx_len) { in vc4_dsi_host_transfer()
1252 if (!wait_for_completion_timeout(&dsi->xfer_completion, in vc4_dsi_host_transfer()
1254 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); in vc4_dsi_host_transfer()
1255 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", in vc4_dsi_host_transfer()
1257 ret = -ETIMEDOUT; in vc4_dsi_host_transfer()
1259 ret = dsi->xfer_result; in vc4_dsi_host_transfer()
1267 if (ret == 0 && msg->rx_len) { in vc4_dsi_host_transfer()
1269 u8 *msg_rx = msg->rx_buf; in vc4_dsi_host_transfer()
1275 if (rxlen != msg->rx_len) { in vc4_dsi_host_transfer()
1277 rxlen, (int)msg->rx_len); in vc4_dsi_host_transfer()
1278 ret = -ENXIO; in vc4_dsi_host_transfer()
1282 for (i = 0; i < msg->rx_len; i++) in vc4_dsi_host_transfer()
1289 if (msg->rx_len > 1) { in vc4_dsi_host_transfer()
1318 dsi->lanes = device->lanes; in vc4_dsi_host_attach()
1319 dsi->channel = device->channel; in vc4_dsi_host_attach()
1320 dsi->mode_flags = device->mode_flags; in vc4_dsi_host_attach()
1322 switch (device->format) { in vc4_dsi_host_attach()
1324 dsi->format = DSI_PFORMAT_RGB888; in vc4_dsi_host_attach()
1325 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1328 dsi->format = DSI_PFORMAT_RGB666; in vc4_dsi_host_attach()
1329 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1332 dsi->format = DSI_PFORMAT_RGB666_PACKED; in vc4_dsi_host_attach()
1333 dsi->divider = 18 / dsi->lanes; in vc4_dsi_host_attach()
1336 dsi->format = DSI_PFORMAT_RGB565; in vc4_dsi_host_attach()
1337 dsi->divider = 16 / dsi->lanes; in vc4_dsi_host_attach()
1340 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", in vc4_dsi_host_attach()
1341 dsi->format); in vc4_dsi_host_attach()
1345 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { in vc4_dsi_host_attach()
1346 dev_err(&dsi->pdev->dev, in vc4_dsi_host_attach()
1351 return component_add(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_attach()
1359 component_del(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_detach()
1377 struct drm_device *drm = encoder->dev; in vc4_dsi_late_register()
1381 ret = vc4_debugfs_add_regset32(drm->primary, dsi->variant->debugfs_name, in vc4_dsi_late_register()
1382 &dsi->regset); in vc4_dsi_late_register()
1416 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1417 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1418 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1429 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type); in dsi_handle_error()
1479 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE : in vc4_dsi_irq_handler()
1482 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1485 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1486 dsi->xfer_result = -ETIMEDOUT; in vc4_dsi_irq_handler()
1494 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1495 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1501 struct device *dev = &dsi->pdev->dev; in vc4_dsi_init_phy_clocks()
1502 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); in vc4_dsi_init_phy_clocks()
1513 dsi->clk_onecell = devm_kzalloc(dev, in vc4_dsi_init_phy_clocks()
1514 sizeof(*dsi->clk_onecell) + in vc4_dsi_init_phy_clocks()
1518 if (!dsi->clk_onecell) in vc4_dsi_init_phy_clocks()
1519 return -ENOMEM; in vc4_dsi_init_phy_clocks()
1520 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); in vc4_dsi_init_phy_clocks()
1523 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; in vc4_dsi_init_phy_clocks()
1529 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name); in vc4_dsi_init_phy_clocks()
1540 fix->mult = 1; in vc4_dsi_init_phy_clocks()
1541 fix->div = phy_clocks[i].div; in vc4_dsi_init_phy_clocks()
1542 fix->hw.init = &init; in vc4_dsi_init_phy_clocks()
1550 ret = devm_clk_hw_register(dev, &fix->hw); in vc4_dsi_init_phy_clocks()
1554 dsi->clk_onecell->hws[i] = &fix->hw; in vc4_dsi_init_phy_clocks()
1557 return of_clk_add_hw_provider(dev->of_node, in vc4_dsi_init_phy_clocks()
1559 dsi->clk_onecell); in vc4_dsi_init_phy_clocks()
1565 struct device *dev = &dsi->pdev->dev; in vc4_dsi_dma_mem_release()
1567 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr); in vc4_dsi_dma_mem_release()
1568 dsi->reg_dma_mem = NULL; in vc4_dsi_dma_mem_release()
1575 dma_release_channel(dsi->reg_dma_chan); in vc4_dsi_dma_chan_release()
1576 dsi->reg_dma_chan = NULL; in vc4_dsi_dma_chan_release()
1589 kref_get(&dsi->kref); in vc4_dsi_get()
1594 kref_put(&dsi->kref, &vc4_dsi_release); in vc4_dsi_put()
1609 struct drm_encoder *encoder = &dsi->encoder.base; in vc4_dsi_bind()
1618 dsi->variant = of_device_get_match_data(dev); in vc4_dsi_bind()
1620 INIT_LIST_HEAD(&dsi->bridge_chain); in vc4_dsi_bind()
1621 dsi->encoder.type = dsi->variant->port ? in vc4_dsi_bind()
1624 dsi->regs = vc4_ioremap_regs(pdev, 0); in vc4_dsi_bind()
1625 if (IS_ERR(dsi->regs)) in vc4_dsi_bind()
1626 return PTR_ERR(dsi->regs); in vc4_dsi_bind()
1628 dsi->regset.base = dsi->regs; in vc4_dsi_bind()
1629 dsi->regset.regs = dsi->variant->regs; in vc4_dsi_bind()
1630 dsi->regset.nregs = dsi->variant->nregs; in vc4_dsi_bind()
1635 return -ENODEV; in vc4_dsi_bind()
1638 /* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to in vc4_dsi_bind()
1642 if (dsi->variant->broken_axi_workaround) { in vc4_dsi_bind()
1645 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, in vc4_dsi_bind()
1646 &dsi->reg_dma_paddr, in vc4_dsi_bind()
1648 if (!dsi->reg_dma_mem) { in vc4_dsi_bind()
1650 return -ENOMEM; in vc4_dsi_bind()
1660 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); in vc4_dsi_bind()
1661 if (IS_ERR(dsi->reg_dma_chan)) { in vc4_dsi_bind()
1662 ret = PTR_ERR(dsi->reg_dma_chan); in vc4_dsi_bind()
1663 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1677 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, in vc4_dsi_bind()
1681 init_completion(&dsi->xfer_completion); in vc4_dsi_bind()
1682 /* At startup enable error-reporting interrupts and nothing else. */ in vc4_dsi_bind()
1687 if (dsi->reg_dma_mem) in vc4_dsi_bind()
1697 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1702 dsi->escape_clock = devm_clk_get(dev, "escape"); in vc4_dsi_bind()
1703 if (IS_ERR(dsi->escape_clock)) { in vc4_dsi_bind()
1704 ret = PTR_ERR(dsi->escape_clock); in vc4_dsi_bind()
1705 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1710 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); in vc4_dsi_bind()
1711 if (IS_ERR(dsi->pll_phy_clock)) { in vc4_dsi_bind()
1712 ret = PTR_ERR(dsi->pll_phy_clock); in vc4_dsi_bind()
1713 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1718 dsi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dsi_bind()
1719 if (IS_ERR(dsi->pixel_clock)) { in vc4_dsi_bind()
1720 ret = PTR_ERR(dsi->pixel_clock); in vc4_dsi_bind()
1721 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1726 dsi->bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0); in vc4_dsi_bind()
1727 if (IS_ERR(dsi->bridge)) in vc4_dsi_bind()
1728 return PTR_ERR(dsi->bridge); in vc4_dsi_bind()
1731 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); in vc4_dsi_bind()
1754 ret = drm_bridge_attach(encoder, dsi->bridge, NULL, 0); in vc4_dsi_bind()
1762 list_splice_init(&encoder->bridge_chain, &dsi->bridge_chain); in vc4_dsi_bind()
1771 struct drm_encoder *encoder = &dsi->encoder.base; in vc4_dsi_unbind()
1777 list_splice_init(&dsi->bridge_chain, &encoder->bridge_chain); in vc4_dsi_unbind()
1787 struct device *dev = &pdev->dev; in vc4_dsi_dev_probe()
1792 return -ENOMEM; in vc4_dsi_dev_probe()
1795 kref_init(&dsi->kref); in vc4_dsi_dev_probe()
1796 dsi->pdev = pdev; in vc4_dsi_dev_probe()
1797 dsi->dsi_host.ops = &vc4_dsi_host_ops; in vc4_dsi_dev_probe()
1798 dsi->dsi_host.dev = dev; in vc4_dsi_dev_probe()
1799 mipi_dsi_host_register(&dsi->dsi_host); in vc4_dsi_dev_probe()
1806 struct device *dev = &pdev->dev; in vc4_dsi_dev_remove()
1809 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_remove()