Lines Matching refs:CRTC_WRITE
53 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) macro
306 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); in vc4_crtc_pixelvalve_reset()
307 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR); in vc4_crtc_pixelvalve_reset()
346 CRTC_WRITE(PV_HORZA, in vc4_crtc_config_pv()
352 CRTC_WRITE(PV_HORZB, in vc4_crtc_config_pv()
358 CRTC_WRITE(PV_VERTA, in vc4_crtc_config_pv()
364 CRTC_WRITE(PV_VERTB, in vc4_crtc_config_pv()
370 CRTC_WRITE(PV_VERTA_EVEN, in vc4_crtc_config_pv()
377 CRTC_WRITE(PV_VERTB_EVEN, in vc4_crtc_config_pv()
388 CRTC_WRITE(PV_V_CONTROL, in vc4_crtc_config_pv()
394 CRTC_WRITE(PV_VSYNCD_EVEN, 0); in vc4_crtc_config_pv()
396 CRTC_WRITE(PV_V_CONTROL, in vc4_crtc_config_pv()
402 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); in vc4_crtc_config_pv()
405 CRTC_WRITE(PV_MUX_CFG, in vc4_crtc_config_pv()
409 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | in vc4_crtc_config_pv()
452 CRTC_WRITE(PV_V_CONTROL, in vc4_crtc_disable()
632 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN); in vc4_crtc_atomic_enable()
640 CRTC_WRITE(PV_V_CONTROL, in vc4_crtc_atomic_enable()
745 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); in vc4_enable_vblank()
761 CRTC_WRITE(PV_INTEN, 0); in vc4_disable_vblank()
810 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); in vc4_crtc_irq_handler()
1365 CRTC_WRITE(PV_INTEN, 0); in vc4_crtc_bind()
1366 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); in vc4_crtc_bind()
1385 CRTC_WRITE(PV_INTEN, 0); in vc4_crtc_unbind()