Lines Matching +full:bcm2835 +full:- +full:hdmi
1 // SPDX-License-Identifier: GPL-2.0-only
21 * image domain can feed either HDMI or the SDTV controller. The
22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
27 * output-specific clock. Since the encoders also directly consume
53 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
54 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
75 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_cob_allocation()
77 /* Top/base are supposed to be 4-pixel aligned, but the in vc4_crtc_get_cob_allocation()
84 return top - base + 4; in vc4_crtc_get_cob_allocation()
93 struct drm_device *dev = crtc->dev; in vc4_crtc_get_scanout_position()
95 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_scanout_position()
97 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); in vc4_crtc_get_scanout_position()
114 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel)); in vc4_crtc_get_scanout_position()
126 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { in vc4_crtc_get_scanout_position()
130 if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2) in vc4_crtc_get_scanout_position()
131 *hpos += mode->crtc_htotal / 2; in vc4_crtc_get_scanout_position()
134 cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel); in vc4_crtc_get_scanout_position()
135 /* This is the offset we need for translating hvs -> pv scanout pos. */ in vc4_crtc_get_scanout_position()
136 fifo_lines = cob_size / mode->crtc_hdisplay; in vc4_crtc_get_scanout_position()
151 * incrementing vpos. Therefore we choose HVS read position - in vc4_crtc_get_scanout_position()
155 *vpos -= fifo_lines + 1; in vc4_crtc_get_scanout_position()
163 * fifo with new lines from the top-most lines of the new framebuffers. in vc4_crtc_get_scanout_position()
169 vblank_lines = mode->vtotal - mode->vdisplay; in vc4_crtc_get_scanout_position()
181 *vpos = -vblank_lines; in vc4_crtc_get_scanout_position()
184 *stime = vc4_crtc->t_vblank; in vc4_crtc_get_scanout_position()
186 *etime = vc4_crtc->t_vblank; in vc4_crtc_get_scanout_position()
214 struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev); in vc4_get_fifo_full_level()
215 u32 fifo_len_bytes = pv_data->fifo_depth; in vc4_get_fifo_full_level()
230 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX; in vc4_get_fifo_full_level()
232 return fifo_len_bytes - 14; in vc4_get_fifo_full_level()
240 if (crtc_data->hvs_output == 5) in vc4_get_fifo_full_level()
256 if (!vc4->is_vc5) in vc4_get_fifo_full_level()
257 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1; in vc4_get_fifo_full_level()
259 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX; in vc4_get_fifo_full_level()
288 WARN_ON(hweight32(state->encoder_mask) > 1); in vc4_get_crtc_encoder()
290 drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) in vc4_get_crtc_encoder()
299 struct drm_device *dev = crtc->dev; in vc4_crtc_pixelvalve_reset()
315 struct drm_device *dev = crtc->dev; in vc4_crtc_config_pv()
320 struct drm_crtc_state *crtc_state = crtc->state; in vc4_crtc_config_pv()
321 struct drm_display_mode *mode = &crtc_state->adjusted_mode; in vc4_crtc_config_pv()
322 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; in vc4_crtc_config_pv()
323 bool is_hdmi = vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0 || in vc4_crtc_config_pv()
324 vc4_encoder->type == VC4_ENCODER_TYPE_HDMI1; in vc4_crtc_config_pv()
325 u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1; in vc4_crtc_config_pv()
326 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || in vc4_crtc_config_pv()
327 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); in vc4_crtc_config_pv()
328 bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1; in vc4_crtc_config_pv()
330 u8 ppc = pv_data->pixels_per_clock; in vc4_crtc_config_pv()
338 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); in vc4_crtc_config_pv()
339 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n", in vc4_crtc_config_pv()
341 drm_print_regset32(&p, &vc4_crtc->regset); in vc4_crtc_config_pv()
347 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, in vc4_crtc_config_pv()
349 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, in vc4_crtc_config_pv()
353 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, in vc4_crtc_config_pv()
355 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
359 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + in vc4_crtc_config_pv()
362 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_crtc_config_pv()
365 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_crtc_config_pv()
367 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
371 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_crtc_config_pv()
372 mode->crtc_vsync_end, in vc4_crtc_config_pv()
374 VC4_SET_FIELD(mode->crtc_vsync_end - in vc4_crtc_config_pv()
375 mode->crtc_vsync_start, in vc4_crtc_config_pv()
378 VC4_SET_FIELD(mode->crtc_vsync_start - in vc4_crtc_config_pv()
379 mode->crtc_vdisplay, in vc4_crtc_config_pv()
381 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
383 /* We set up first field even mode for HDMI. VEC's in vc4_crtc_config_pv()
392 VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc), in vc4_crtc_config_pv()
402 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); in vc4_crtc_config_pv()
404 if (vc4->is_vc5) in vc4_crtc_config_pv()
412 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | in vc4_crtc_config_pv()
416 VC4_SET_FIELD(vc4_encoder->clock_select, in vc4_crtc_config_pv()
420 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); in vc4_crtc_config_pv()
421 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n", in vc4_crtc_config_pv()
423 drm_print_regset32(&p, &vc4_crtc->regset); in vc4_crtc_config_pv()
432 struct vc4_hvs *hvs = vc4->hvs; in require_hvs_enabled()
445 struct drm_device *dev = crtc->dev; in vc4_crtc_disable()
450 return -ENODEV; in vc4_crtc_disable()
459 * unflushable FIFO between the pixelvalve and the HDMI in vc4_crtc_disable()
475 if (vc4_encoder && vc4_encoder->post_crtc_disable) in vc4_crtc_disable()
476 vc4_encoder->post_crtc_disable(encoder, state); in vc4_crtc_disable()
479 vc4_hvs_stop_channel(vc4->hvs, channel); in vc4_crtc_disable()
481 if (vc4_encoder && vc4_encoder->post_crtc_powerdown) in vc4_crtc_disable()
482 vc4_encoder->post_crtc_powerdown(encoder, state); in vc4_crtc_disable()
494 drm_for_each_encoder(encoder, crtc->dev) { in vc4_crtc_get_encoder_by_type()
497 if (vc4_encoder->type == type) in vc4_crtc_get_encoder_by_type()
506 struct drm_device *drm = crtc->dev; in vc4_crtc_disable_at_boot()
517 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node, in vc4_crtc_disable_at_boot()
518 "brcm,bcm2711-pixelvalve2") || in vc4_crtc_disable_at_boot()
519 of_device_is_compatible(vc4_crtc->pdev->dev.of_node, in vc4_crtc_disable_at_boot()
520 "brcm,bcm2711-pixelvalve4"))) in vc4_crtc_disable_at_boot()
529 channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output); in vc4_crtc_disable_at_boot()
538 encoder_type = pv_data->encoder_types[encoder_sel]; in vc4_crtc_disable_at_boot()
544 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); in vc4_crtc_disable_at_boot()
563 struct drm_device *dev = crtc->dev; in vc4_crtc_send_vblank()
566 if (!crtc->state || !crtc->state->event) in vc4_crtc_send_vblank()
569 spin_lock_irqsave(&dev->event_lock, flags); in vc4_crtc_send_vblank()
570 drm_crtc_send_vblank_event(crtc, crtc->state->event); in vc4_crtc_send_vblank()
571 crtc->state->event = NULL; in vc4_crtc_send_vblank()
572 spin_unlock_irqrestore(&dev->event_lock, flags); in vc4_crtc_send_vblank()
582 struct drm_device *dev = crtc->dev; in vc4_crtc_atomic_disable()
585 crtc->name, crtc->base.id, encoder->name, encoder->base.id); in vc4_crtc_atomic_disable()
592 vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel); in vc4_crtc_atomic_disable()
606 struct drm_device *dev = crtc->dev; in vc4_crtc_atomic_enable()
613 crtc->name, crtc->base.id, encoder->name, encoder->base.id); in vc4_crtc_atomic_enable()
627 if (vc4_encoder->pre_crtc_configure) in vc4_crtc_atomic_enable()
628 vc4_encoder->pre_crtc_configure(encoder, state); in vc4_crtc_atomic_enable()
634 if (vc4_encoder->pre_crtc_enable) in vc4_crtc_atomic_enable()
635 vc4_encoder->pre_crtc_enable(encoder, state); in vc4_crtc_atomic_enable()
643 if (vc4_encoder->post_crtc_enable) in vc4_crtc_atomic_enable()
644 vc4_encoder->post_crtc_enable(encoder, state); in vc4_crtc_atomic_enable()
653 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { in vc4_crtc_mode_valid()
655 crtc->base.id); in vc4_crtc_mode_valid()
671 *left = vc4_state->margins.left; in vc4_crtc_get_margins()
672 *right = vc4_state->margins.right; in vc4_crtc_get_margins()
673 *top = vc4_state->margins.top; in vc4_crtc_get_margins()
674 *bottom = vc4_state->margins.bottom; in vc4_crtc_get_margins()
681 for_each_new_connector_in_state(state->state, conn, conn_state, i) { in vc4_crtc_get_margins()
682 if (conn_state->crtc != state->crtc) in vc4_crtc_get_margins()
685 *left = conn_state->tv.margins.left; in vc4_crtc_get_margins()
686 *right = conn_state->tv.margins.right; in vc4_crtc_get_margins()
687 *top = conn_state->tv.margins.top; in vc4_crtc_get_margins()
688 *bottom = conn_state->tv.margins.bottom; in vc4_crtc_get_margins()
710 const struct drm_display_mode *mode = &crtc_state->adjusted_mode; in vc4_crtc_atomic_check()
713 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) { in vc4_crtc_atomic_check()
714 vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000, in vc4_crtc_atomic_check()
715 mode->clock * 9 / 10) * 1000; in vc4_crtc_atomic_check()
717 vc4_state->hvs_load = mode->clock * 1000; in vc4_crtc_atomic_check()
723 if (conn_state->crtc != crtc) in vc4_crtc_atomic_check()
726 vc4_state->margins.left = conn_state->tv.margins.left; in vc4_crtc_atomic_check()
727 vc4_state->margins.right = conn_state->tv.margins.right; in vc4_crtc_atomic_check()
728 vc4_state->margins.top = conn_state->tv.margins.top; in vc4_crtc_atomic_check()
729 vc4_state->margins.bottom = conn_state->tv.margins.bottom; in vc4_crtc_atomic_check()
739 struct drm_device *dev = crtc->dev; in vc4_enable_vblank()
743 return -ENODEV; in vc4_enable_vblank()
755 struct drm_device *dev = crtc->dev; in vc4_disable_vblank()
768 struct drm_crtc *crtc = &vc4_crtc->base; in vc4_crtc_handle_page_flip()
769 struct drm_device *dev = crtc->dev; in vc4_crtc_handle_page_flip()
771 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_handle_page_flip()
772 u32 chan = vc4_crtc->current_hvs_channel; in vc4_crtc_handle_page_flip()
775 spin_lock_irqsave(&dev->event_lock, flags); in vc4_crtc_handle_page_flip()
776 spin_lock(&vc4_crtc->irq_lock); in vc4_crtc_handle_page_flip()
777 if (vc4_crtc->event && in vc4_crtc_handle_page_flip()
778 (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) || in vc4_crtc_handle_page_flip()
779 vc4_crtc->feeds_txp)) { in vc4_crtc_handle_page_flip()
780 drm_crtc_send_vblank_event(crtc, vc4_crtc->event); in vc4_crtc_handle_page_flip()
781 vc4_crtc->event = NULL; in vc4_crtc_handle_page_flip()
792 spin_unlock(&vc4_crtc->irq_lock); in vc4_crtc_handle_page_flip()
793 spin_unlock_irqrestore(&dev->event_lock, flags); in vc4_crtc_handle_page_flip()
798 crtc->t_vblank = ktime_get(); in vc4_crtc_handle_vblank()
799 drm_crtc_handle_vblank(&crtc->base); in vc4_crtc_handle_vblank()
836 struct drm_crtc *crtc = flip_state->crtc; in vc4_async_page_flip_complete()
837 struct drm_device *dev = crtc->dev; in vc4_async_page_flip_complete()
838 struct drm_plane *plane = crtc->primary; in vc4_async_page_flip_complete()
840 vc4_plane_async_set_fb(plane, flip_state->fb); in vc4_async_page_flip_complete()
841 if (flip_state->event) { in vc4_async_page_flip_complete()
844 spin_lock_irqsave(&dev->event_lock, flags); in vc4_async_page_flip_complete()
845 drm_crtc_send_vblank_event(crtc, flip_state->event); in vc4_async_page_flip_complete()
846 spin_unlock_irqrestore(&dev->event_lock, flags); in vc4_async_page_flip_complete()
850 drm_framebuffer_put(flip_state->fb); in vc4_async_page_flip_complete()
852 if (flip_state->old_fb) in vc4_async_page_flip_complete()
853 drm_framebuffer_put(flip_state->old_fb); in vc4_async_page_flip_complete()
864 if (flip_state->old_fb) { in vc4_async_page_flip_seqno_complete()
866 drm_fb_dma_get_gem_obj(flip_state->old_fb, 0); in vc4_async_page_flip_seqno_complete()
867 bo = to_vc4_bo(&dma_bo->base); in vc4_async_page_flip_seqno_complete()
877 * FIXME: we should move to generic async-page-flip when in vc4_async_page_flip_seqno_complete()
879 * hand-made cleanup_fb() logic. in vc4_async_page_flip_seqno_complete()
898 struct drm_framebuffer *fb = flip_state->fb; in vc4_async_set_fence_cb()
904 if (!vc4->is_vc5) { in vc4_async_set_fence_cb()
905 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base); in vc4_async_set_fence_cb()
907 return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno, in vc4_async_set_fence_cb()
911 ret = dma_resv_get_singleton(dma_bo->base.resv, DMA_RESV_USAGE_READ, &fence); in vc4_async_set_fence_cb()
917 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence); in vc4_async_set_fence_cb()
922 if (dma_fence_add_callback(fence, &flip_state->cb.fence, in vc4_async_set_fence_cb()
924 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence); in vc4_async_set_fence_cb()
935 struct drm_device *dev = crtc->dev; in vc4_async_page_flip_common()
936 struct drm_plane *plane = crtc->primary; in vc4_async_page_flip_common()
941 return -ENOMEM; in vc4_async_page_flip_common()
944 flip_state->fb = fb; in vc4_async_page_flip_common()
945 flip_state->crtc = crtc; in vc4_async_page_flip_common()
946 flip_state->event = event; in vc4_async_page_flip_common()
952 * FIXME: we should move to generic async-page-flip when it's in vc4_async_page_flip_common()
953 * available, so that we can get rid of this hand-made cleanup_fb() in vc4_async_page_flip_common()
956 flip_state->old_fb = plane->state->fb; in vc4_async_page_flip_common()
957 if (flip_state->old_fb) in vc4_async_page_flip_common()
958 drm_framebuffer_get(flip_state->old_fb); in vc4_async_page_flip_common()
966 drm_atomic_set_fb_for_plane(plane->state, fb); in vc4_async_page_flip_common()
974 /* Implements async (non-vblank-synced) page flips.
985 struct drm_device *dev = crtc->dev; in vc4_async_page_flip()
988 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base); in vc4_async_page_flip()
991 if (WARN_ON_ONCE(vc4->is_vc5)) in vc4_async_page_flip()
992 return -ENODEV; in vc4_async_page_flip()
997 * plane is later updated through the non-async path. in vc4_async_page_flip()
999 * FIXME: we should move to generic async-page-flip when in vc4_async_page_flip()
1001 * hand-made prepare_fb() logic. in vc4_async_page_flip()
1031 struct drm_device *dev = crtc->dev; in vc4_page_flip()
1034 if (vc4->is_vc5) in vc4_page_flip()
1051 old_vc4_state = to_vc4_crtc_state(crtc->state); in vc4_crtc_duplicate_state()
1052 vc4_state->margins = old_vc4_state->margins; in vc4_crtc_duplicate_state()
1053 vc4_state->assigned_channel = old_vc4_state->assigned_channel; in vc4_crtc_duplicate_state()
1055 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); in vc4_crtc_duplicate_state()
1056 return &vc4_state->base; in vc4_crtc_duplicate_state()
1062 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); in vc4_crtc_destroy_state()
1065 if (drm_mm_node_allocated(&vc4_state->mm)) { in vc4_crtc_destroy_state()
1068 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); in vc4_crtc_destroy_state()
1069 drm_mm_remove_node(&vc4_state->mm); in vc4_crtc_destroy_state()
1070 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); in vc4_crtc_destroy_state()
1081 if (crtc->state) in vc4_crtc_reset()
1082 vc4_crtc_destroy_state(crtc, crtc->state); in vc4_crtc_reset()
1086 crtc->state = NULL; in vc4_crtc_reset()
1090 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; in vc4_crtc_reset()
1091 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base); in vc4_crtc_reset()
1096 struct drm_device *drm = crtc->dev; in vc4_crtc_late_register()
1101 ret = vc4_debugfs_add_regset32(drm->primary, crtc_data->debugfs_name, in vc4_crtc_late_register()
1102 &vc4_crtc->regset); in vc4_crtc_late_register()
1244 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1245 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1246 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1247 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1248 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1249 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1250 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1251 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1260 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types; in vc4_set_crtc_possible_masks()
1267 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) in vc4_set_crtc_possible_masks()
1271 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) { in vc4_set_crtc_possible_masks()
1272 if (vc4_encoder->type == encoder_types[i]) { in vc4_set_crtc_possible_masks()
1273 vc4_encoder->clock_select = i; in vc4_set_crtc_possible_masks()
1274 encoder->possible_crtcs |= drm_crtc_mask(crtc); in vc4_set_crtc_possible_masks()
1286 struct drm_crtc *crtc = &vc4_crtc->base; in vc4_crtc_init()
1299 dev_err(drm->dev, "failed to construct primary plane\n"); in vc4_crtc_init()
1303 spin_lock_init(&vc4_crtc->irq_lock); in vc4_crtc_init()
1311 if (!vc4->is_vc5) { in vc4_crtc_init()
1312 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); in vc4_crtc_init()
1314 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); in vc4_crtc_init()
1319 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); in vc4_crtc_init()
1322 for (i = 0; i < crtc->gamma_size; i++) { in vc4_crtc_init()
1323 vc4_crtc->lut_r[i] = i; in vc4_crtc_init()
1324 vc4_crtc->lut_g[i] = i; in vc4_crtc_init()
1325 vc4_crtc->lut_b[i] = i; in vc4_crtc_init()
1342 return -ENOMEM; in vc4_crtc_bind()
1343 crtc = &vc4_crtc->base; in vc4_crtc_bind()
1347 return -ENODEV; in vc4_crtc_bind()
1348 vc4_crtc->data = &pv_data->base; in vc4_crtc_bind()
1349 vc4_crtc->pdev = pdev; in vc4_crtc_bind()
1351 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); in vc4_crtc_bind()
1352 if (IS_ERR(vc4_crtc->regs)) in vc4_crtc_bind()
1353 return PTR_ERR(vc4_crtc->regs); in vc4_crtc_bind()
1355 vc4_crtc->regset.base = vc4_crtc->regs; in vc4_crtc_bind()
1356 vc4_crtc->regset.regs = crtc_regs; in vc4_crtc_bind()
1357 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs); in vc4_crtc_bind()
1397 return component_add(&pdev->dev, &vc4_crtc_ops); in vc4_crtc_dev_probe()
1402 component_del(&pdev->dev, &vc4_crtc_ops); in vc4_crtc_dev_remove()