Lines Matching +full:4 +full:- +full:ch
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
18 * bit group |dev|wb |mrg0|mrg1|mrg2|mrg3|plane0-3| <unused> |
20 * bit number|0 |1-3|4-7 |8-11| 12-19 | 20-23 | 24-31 |
36 #define DSS_IRQ_VP_BIT_N(ch, bit) (4 + 4 * (ch) + (bit)) argument
40 #define DSS_IRQ_VP_BIT(ch, bit) BIT(DSS_IRQ_VP_BIT_N((ch), (bit))) argument
44 static inline dispc_irq_t DSS_IRQ_VP_MASK(u32 ch) in DSS_IRQ_VP_MASK() argument
46 return GENMASK(DSS_IRQ_VP_BIT_N((ch), 3), DSS_IRQ_VP_BIT_N((ch), 0)); in DSS_IRQ_VP_MASK()
55 #define DSS_IRQ_VP_FRAME_DONE(ch) DSS_IRQ_VP_BIT((ch), 0) argument
56 #define DSS_IRQ_VP_VSYNC_EVEN(ch) DSS_IRQ_VP_BIT((ch), 1) argument
57 #define DSS_IRQ_VP_VSYNC_ODD(ch) DSS_IRQ_VP_BIT((ch), 2) argument
58 #define DSS_IRQ_VP_SYNC_LOST(ch) DSS_IRQ_VP_BIT((ch), 3) argument