Lines Matching +full:k2g +full:- +full:dss
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
9 #include <linux/dma-mapping.h>
14 #include <linux/media-bus-format.h>
81 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
84 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
157 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
160 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
246 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
249 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
315 iowrite32(val, dispc->base_common + reg); in dispc_write()
320 return ioread32(dispc->base_common + reg); in dispc_read()
326 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
333 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
341 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
348 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_read()
356 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_write()
363 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_read()
375 return ((1 << (start - end + 1)) - 1) << end; in FLD_MASK()
684 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_clear_irqstatus()
690 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_clear_irqstatus()
696 if (dispc->feat->subrev == DISPC_K2G) in dispc_k3_clear_irqstatus()
711 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_and_clear_irqstatus()
714 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_and_clear_irqstatus()
727 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_irqenable()
730 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_irqenable()
748 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_set_irqenable()
756 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_set_irqenable()
776 switch (dispc->feat->subrev) { in dispc_read_and_clear_irqstatus()
790 switch (dispc->feat->subrev) { in dispc_set_irqenable()
846 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_bus_check()
847 tstate->bus_flags); in dispc_vp_bus_check()
849 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", in dispc_vp_bus_check()
850 __func__, tstate->bus_format); in dispc_vp_bus_check()
851 return -EINVAL; in dispc_vp_bus_check()
854 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && in dispc_vp_bus_check()
855 fmt->is_oldi_fmt) { in dispc_vp_bus_check()
856 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", in dispc_vp_bus_check()
857 __func__, dispc->feat->vp_name[hw_videoport]); in dispc_vp_bus_check()
858 return -EINVAL; in dispc_vp_bus_check()
868 if (WARN_ON(!dispc->oldi_io_ctrl)) in dispc_oldi_tx_power()
871 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, in dispc_oldi_tx_power()
873 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, in dispc_oldi_tx_power()
875 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, in dispc_oldi_tx_power()
877 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, in dispc_oldi_tx_power()
879 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, in dispc_oldi_tx_power()
921 if (fmt->data_width == 24) in dispc_enable_oldi()
923 else if (fmt->data_width != 18) in dispc_enable_oldi()
924 dev_warn(dispc->dev, "%s: %d port width not supported\n", in dispc_enable_oldi()
925 __func__, fmt->data_width); in dispc_enable_oldi()
929 oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode_reg_val, 3, 1); in dispc_enable_oldi()
942 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", in dispc_enable_oldi()
952 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_prepare()
953 tstate->bus_flags); in dispc_vp_prepare()
958 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_prepare()
968 const struct drm_display_mode *mode = &state->adjusted_mode; in dispc_vp_enable()
974 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_enable()
975 tstate->bus_flags); in dispc_vp_enable()
980 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); in dispc_vp_enable()
982 hfp = mode->hsync_start - mode->hdisplay; in dispc_vp_enable()
983 hsw = mode->hsync_end - mode->hsync_start; in dispc_vp_enable()
984 hbp = mode->htotal - mode->hsync_end; in dispc_vp_enable()
986 vfp = mode->vsync_start - mode->vdisplay; in dispc_vp_enable()
987 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_enable()
988 vbp = mode->vtotal - mode->vsync_end; in dispc_vp_enable()
991 FLD_VAL(hsw - 1, 7, 0) | in dispc_vp_enable()
992 FLD_VAL(hfp - 1, 19, 8) | in dispc_vp_enable()
993 FLD_VAL(hbp - 1, 31, 20)); in dispc_vp_enable()
996 FLD_VAL(vsw - 1, 7, 0) | in dispc_vp_enable()
1000 ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); in dispc_vp_enable()
1002 ihs = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); in dispc_vp_enable()
1004 ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW); in dispc_vp_enable()
1006 ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); in dispc_vp_enable()
1011 rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE); in dispc_vp_enable()
1017 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) in dispc_vp_enable()
1030 FLD_VAL(mode->hdisplay - 1, 11, 0) | in dispc_vp_enable()
1031 FLD_VAL(mode->vdisplay - 1, 27, 16)); in dispc_vp_enable()
1043 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_unprepare()
1122 bus_type = dispc->feat->vp_bus_type[hw_videoport]; in dispc_vp_mode_valid()
1124 max_pclk = dispc->feat->max_pclk_khz[bus_type]; in dispc_vp_mode_valid()
1129 if (mode->clock < dispc->feat->min_pclk_khz) in dispc_vp_mode_valid()
1132 if (mode->clock > max_pclk) in dispc_vp_mode_valid()
1135 if (mode->hdisplay > 4096) in dispc_vp_mode_valid()
1138 if (mode->vdisplay > 4096) in dispc_vp_mode_valid()
1142 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dispc_vp_mode_valid()
1148 * - YUV output selected (BT656, BT1120) in dispc_vp_mode_valid()
1149 * - Dithering enabled in dispc_vp_mode_valid()
1150 * - TDM with TDMCycleFormat == 3 in dispc_vp_mode_valid()
1153 if ((mode->hdisplay % 2) != 0) in dispc_vp_mode_valid()
1156 hfp = mode->hsync_start - mode->hdisplay; in dispc_vp_mode_valid()
1157 hsw = mode->hsync_end - mode->hsync_start; in dispc_vp_mode_valid()
1158 hbp = mode->htotal - mode->hsync_end; in dispc_vp_mode_valid()
1160 vfp = mode->vsync_start - mode->vdisplay; in dispc_vp_mode_valid()
1161 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_mode_valid()
1162 vbp = mode->vtotal - mode->vsync_end; in dispc_vp_mode_valid()
1173 if (dispc->memory_bandwidth_limit) { in dispc_vp_mode_valid()
1177 bandwidth = 1000 * mode->clock; in dispc_vp_mode_valid()
1178 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; in dispc_vp_mode_valid()
1179 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); in dispc_vp_mode_valid()
1181 if (dispc->memory_bandwidth_limit < bandwidth) in dispc_vp_mode_valid()
1190 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); in dispc_vp_enable_clk()
1193 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, in dispc_vp_enable_clk()
1201 clk_disable_unprepare(dispc->vp_clk[hw_videoport]); in dispc_vp_disable_clk()
1213 return (unsigned int)(abs(((rr - r) * 100) / r)); in dispc_pclk_diff()
1222 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); in dispc_vp_set_clk_rate()
1224 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", in dispc_vp_set_clk_rate()
1229 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); in dispc_vp_set_clk_rate()
1232 dev_warn(dispc->dev, in dispc_vp_set_clk_rate()
1236 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", in dispc_vp_set_clk_rate()
1237 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); in dispc_vp_set_clk_rate()
1247 /* On k2g there is only one plane and no need for ovr */ in dispc_k2g_ovr_set_plane()
1279 switch (dispc->feat->subrev) { in dispc_ovr_set_plane()
1301 if (dispc->feat->subrev == DISPC_K2G) in dispc_ovr_enable_layer()
1342 regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); in dispc_csc_offset_regval()
1343 regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); in dispc_csc_offset_regval()
1344 regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); in dispc_csc_offset_regval()
1352 regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); in dispc_csc_yuv2rgb_regval()
1353 regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); in dispc_csc_yuv2rgb_regval()
1354 regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]); in dispc_csc_yuv2rgb_regval()
1355 regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]); in dispc_csc_yuv2rgb_regval()
1356 regval[4] = CVAL(csc->m[CSC_BCB], 0); in dispc_csc_yuv2rgb_regval()
1364 regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]); in dispc_csc_rgb2yuv_regval()
1365 regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]); in dispc_csc_rgb2yuv_regval()
1366 regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]); in dispc_csc_rgb2yuv_regval()
1367 regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]); in dispc_csc_rgb2yuv_regval()
1368 regval[4] = CVAL(csc->m[CSC_CBB], 0); in dispc_csc_rgb2yuv_regval()
1376 regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]); in dispc_csc_cpr_regval()
1377 regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]); in dispc_csc_cpr_regval()
1378 regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]); in dispc_csc_cpr_regval()
1379 regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]); in dispc_csc_cpr_regval()
1380 regval[4] = CVAL(csc->m[CSC_BB], 0); in dispc_csc_cpr_regval()
1394 DISPC_VID_CSC_COEF(6), /* K2G has no post offset support */ in dispc_k2g_vid_write_csc()
1399 csc->to_regval(csc, regval); in dispc_k2g_vid_write_csc()
1402 dev_warn(dispc->dev, "%s: No post offset support for %s\n", in dispc_k2g_vid_write_csc()
1403 __func__, csc->name); in dispc_k2g_vid_write_csc()
1422 csc->to_regval(csc, regval); in dispc_k3_vid_write_csc()
1429 /* YUV -> RGB, ITU-R BT.601, full range */
1433 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/
1435 { 0, -2048, -2048, }, /* full range */
1441 /* YUV -> RGB, ITU-R BT.601, limited range */
1445 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/
1447 { -256, -2048, -2048, }, /* limited range */
1453 /* YUV -> RGB, ITU-R BT.709, full range */
1457 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/
1459 { 0, -2048, -2048, }, /* full range */
1465 /* YUV -> RGB, ITU-R BT.709, limited range */
1469 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/
1471 { -256, -2048, -2048, }, /* limited range */
1512 coef = dispc_find_csc(state->color_encoding, state->color_range); in dispc_vid_csc_setup()
1514 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", in dispc_vid_csc_setup()
1515 __func__, state->color_encoding, state->color_range); in dispc_vid_csc_setup()
1519 if (dispc->feat->subrev == DISPC_K2G) in dispc_vid_csc_setup()
1569 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); in dispc_vid_write_fir_coefs()
1575 u16 c0 = coefs->c0[phase]; in dispc_vid_write_fir_coefs()
1585 c1 = coefs->c1[phase]; in dispc_vid_write_fir_coefs()
1586 c2 = coefs->c2[phase]; in dispc_vid_write_fir_coefs()
1619 const struct dispc_features_scaling *f = &dispc->feat->scaling; in dispc_vid_calc_scaling()
1620 u32 fourcc = state->fb->format->format; in dispc_vid_calc_scaling()
1621 u32 in_width_max_5tap = f->in_width_max_5tap_rgb; in dispc_vid_calc_scaling()
1622 u32 in_width_max_3tap = f->in_width_max_3tap_rgb; in dispc_vid_calc_scaling()
1627 sp->xinc = 1; in dispc_vid_calc_scaling()
1628 sp->yinc = 1; in dispc_vid_calc_scaling()
1629 sp->in_w = state->src_w >> 16; in dispc_vid_calc_scaling()
1630 sp->in_w_uv = sp->in_w; in dispc_vid_calc_scaling()
1631 sp->in_h = state->src_h >> 16; in dispc_vid_calc_scaling()
1632 sp->in_h_uv = sp->in_h; in dispc_vid_calc_scaling()
1634 sp->scale_x = sp->in_w != state->crtc_w; in dispc_vid_calc_scaling()
1635 sp->scale_y = sp->in_h != state->crtc_h; in dispc_vid_calc_scaling()
1638 in_width_max_5tap = f->in_width_max_5tap_yuv; in dispc_vid_calc_scaling()
1639 in_width_max_3tap = f->in_width_max_3tap_yuv; in dispc_vid_calc_scaling()
1641 sp->in_w_uv >>= 1; in dispc_vid_calc_scaling()
1642 sp->scale_x = true; in dispc_vid_calc_scaling()
1645 sp->in_h_uv >>= 1; in dispc_vid_calc_scaling()
1646 sp->scale_y = true; in dispc_vid_calc_scaling()
1651 if ((!sp->scale_x && !sp->scale_y) || lite_plane) in dispc_vid_calc_scaling()
1654 if (sp->in_w > in_width_max_5tap) { in dispc_vid_calc_scaling()
1655 sp->five_taps = false; in dispc_vid_calc_scaling()
1657 downscale_limit = f->downscale_limit_3tap; in dispc_vid_calc_scaling()
1659 sp->five_taps = true; in dispc_vid_calc_scaling()
1661 downscale_limit = f->downscale_limit_5tap; in dispc_vid_calc_scaling()
1664 if (sp->scale_x) { in dispc_vid_calc_scaling()
1665 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); in dispc_vid_calc_scaling()
1667 if (sp->fir_xinc < dispc_calc_fir_inc(1, f->upscale_limit)) { in dispc_vid_calc_scaling()
1668 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1669 "%s: X-scaling factor %u/%u > %u\n", in dispc_vid_calc_scaling()
1670 __func__, state->crtc_w, state->src_w >> 16, in dispc_vid_calc_scaling()
1671 f->upscale_limit); in dispc_vid_calc_scaling()
1672 return -EINVAL; in dispc_vid_calc_scaling()
1675 if (sp->fir_xinc >= dispc_calc_fir_inc(downscale_limit, 1)) { in dispc_vid_calc_scaling()
1676 sp->xinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_w, in dispc_vid_calc_scaling()
1677 state->crtc_w), in dispc_vid_calc_scaling()
1680 if (sp->xinc > f->xinc_max) { in dispc_vid_calc_scaling()
1681 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1682 "%s: X-scaling factor %u/%u < 1/%u\n", in dispc_vid_calc_scaling()
1683 __func__, state->crtc_w, in dispc_vid_calc_scaling()
1684 state->src_w >> 16, in dispc_vid_calc_scaling()
1685 downscale_limit * f->xinc_max); in dispc_vid_calc_scaling()
1686 return -EINVAL; in dispc_vid_calc_scaling()
1689 sp->in_w = (state->src_w >> 16) / sp->xinc; in dispc_vid_calc_scaling()
1692 while (sp->in_w > in_width_max) { in dispc_vid_calc_scaling()
1693 sp->xinc++; in dispc_vid_calc_scaling()
1694 sp->in_w = (state->src_w >> 16) / sp->xinc; in dispc_vid_calc_scaling()
1697 if (sp->xinc > f->xinc_max) { in dispc_vid_calc_scaling()
1698 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1700 state->src_w >> 16, in_width_max * f->xinc_max); in dispc_vid_calc_scaling()
1701 return -EINVAL; in dispc_vid_calc_scaling()
1710 sp->in_w &= ~1; in dispc_vid_calc_scaling()
1712 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); in dispc_vid_calc_scaling()
1715 if (sp->scale_y) { in dispc_vid_calc_scaling()
1716 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, state->crtc_h); in dispc_vid_calc_scaling()
1718 if (sp->fir_yinc < dispc_calc_fir_inc(1, f->upscale_limit)) { in dispc_vid_calc_scaling()
1719 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1720 "%s: Y-scaling factor %u/%u > %u\n", in dispc_vid_calc_scaling()
1721 __func__, state->crtc_h, state->src_h >> 16, in dispc_vid_calc_scaling()
1722 f->upscale_limit); in dispc_vid_calc_scaling()
1723 return -EINVAL; in dispc_vid_calc_scaling()
1726 if (sp->fir_yinc >= dispc_calc_fir_inc(downscale_limit, 1)) { in dispc_vid_calc_scaling()
1727 sp->yinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_h, in dispc_vid_calc_scaling()
1728 state->crtc_h), in dispc_vid_calc_scaling()
1731 sp->in_h /= sp->yinc; in dispc_vid_calc_scaling()
1732 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, in dispc_vid_calc_scaling()
1733 state->crtc_h); in dispc_vid_calc_scaling()
1737 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1738 "%s: %ux%u decim %ux%u -> %ux%u firinc %u.%03ux%u.%03u taps %u -> %ux%u\n", in dispc_vid_calc_scaling()
1739 __func__, state->src_w >> 16, state->src_h >> 16, in dispc_vid_calc_scaling()
1740 sp->xinc, sp->yinc, sp->in_w, sp->in_h, in dispc_vid_calc_scaling()
1741 sp->fir_xinc / 0x200000u, in dispc_vid_calc_scaling()
1742 ((sp->fir_xinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, in dispc_vid_calc_scaling()
1743 sp->fir_yinc / 0x200000u, in dispc_vid_calc_scaling()
1744 ((sp->fir_yinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, in dispc_vid_calc_scaling()
1745 sp->five_taps ? 5 : 3, in dispc_vid_calc_scaling()
1746 state->crtc_w, state->crtc_h); in dispc_vid_calc_scaling()
1749 if (sp->scale_x) { in dispc_vid_calc_scaling()
1750 sp->in_w_uv /= sp->xinc; in dispc_vid_calc_scaling()
1751 sp->fir_xinc_uv = dispc_calc_fir_inc(sp->in_w_uv, in dispc_vid_calc_scaling()
1752 state->crtc_w); in dispc_vid_calc_scaling()
1753 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1754 sp->fir_xinc_uv, in dispc_vid_calc_scaling()
1757 if (sp->scale_y) { in dispc_vid_calc_scaling()
1758 sp->in_h_uv /= sp->yinc; in dispc_vid_calc_scaling()
1759 sp->fir_yinc_uv = dispc_calc_fir_inc(sp->in_h_uv, in dispc_vid_calc_scaling()
1760 state->crtc_h); in dispc_vid_calc_scaling()
1761 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1762 sp->fir_yinc_uv, in dispc_vid_calc_scaling()
1763 sp->five_taps); in dispc_vid_calc_scaling()
1767 if (sp->scale_x) in dispc_vid_calc_scaling()
1768 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, in dispc_vid_calc_scaling()
1771 if (sp->scale_y) in dispc_vid_calc_scaling()
1772 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, in dispc_vid_calc_scaling()
1773 sp->five_taps); in dispc_vid_calc_scaling()
1785 sp->scale_x, 7, 7); in dispc_vid_set_scaling()
1789 sp->scale_y, 8, 8); in dispc_vid_set_scaling()
1792 if (!sp->scale_x && !sp->scale_y) in dispc_vid_set_scaling()
1795 /* VERTICAL 5-TAPS */ in dispc_vid_set_scaling()
1797 sp->five_taps, 21, 21); in dispc_vid_set_scaling()
1800 if (sp->scale_x) { in dispc_vid_set_scaling()
1802 sp->fir_xinc_uv); in dispc_vid_set_scaling()
1805 sp->xcoef_uv); in dispc_vid_set_scaling()
1807 if (sp->scale_y) { in dispc_vid_set_scaling()
1809 sp->fir_yinc_uv); in dispc_vid_set_scaling()
1812 sp->ycoef_uv); in dispc_vid_set_scaling()
1816 if (sp->scale_x) { in dispc_vid_set_scaling()
1817 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); in dispc_vid_set_scaling()
1820 sp->xcoef); in dispc_vid_set_scaling()
1823 if (sp->scale_y) { in dispc_vid_set_scaling()
1824 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); in dispc_vid_set_scaling()
1826 DISPC_VID_FIR_COEF_VERT, sp->ycoef); in dispc_vid_set_scaling()
1897 WARN_ON(!dispc->fourccs); in dispc_plane_formats()
1899 *len = dispc->num_fourccs; in dispc_plane_formats()
1901 return dispc->fourccs; in dispc_plane_formats()
1909 return 1 + (pixels - 1) * ps; in pixinc()
1911 return 1 - (-pixels + 1) * ps; in pixinc()
1921 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_check()
1922 u32 fourcc = state->fb->format->format; in dispc_plane_check()
1923 bool need_scaling = state->src_w >> 16 != state->crtc_w || in dispc_plane_check()
1924 state->src_h >> 16 != state->crtc_h; in dispc_plane_check()
1929 if (!dispc_find_csc(state->color_encoding, in dispc_plane_check()
1930 state->color_range)) { in dispc_plane_check()
1931 dev_dbg(dispc->dev, in dispc_plane_check()
1933 __func__, state->color_encoding, in dispc_plane_check()
1934 state->color_range, hw_plane); in dispc_plane_check()
1935 return -EINVAL; in dispc_plane_check()
1941 dev_dbg(dispc->dev, in dispc_plane_check()
1944 state->src_w >> 16, state->src_h >> 16, in dispc_plane_check()
1945 state->crtc_w, state->crtc_h); in dispc_plane_check()
1946 return -EINVAL; in dispc_plane_check()
1959 struct drm_framebuffer *fb = state->fb; in dispc_plane_state_dma_addr()
1961 u32 x = state->src_x >> 16; in dispc_plane_state_dma_addr()
1962 u32 y = state->src_y >> 16; in dispc_plane_state_dma_addr()
1964 gem = drm_fb_dma_get_gem_obj(state->fb, 0); in dispc_plane_state_dma_addr()
1966 return gem->dma_addr + fb->offsets[0] + x * fb->format->cpp[0] + in dispc_plane_state_dma_addr()
1967 y * fb->pitches[0]; in dispc_plane_state_dma_addr()
1973 struct drm_framebuffer *fb = state->fb; in dispc_plane_state_p_uv_addr()
1975 u32 x = state->src_x >> 16; in dispc_plane_state_p_uv_addr()
1976 u32 y = state->src_y >> 16; in dispc_plane_state_p_uv_addr()
1978 if (WARN_ON(state->fb->format->num_planes != 2)) in dispc_plane_state_p_uv_addr()
1983 return gem->dma_addr + fb->offsets[1] + in dispc_plane_state_p_uv_addr()
1984 (x * fb->format->cpp[1] / fb->format->hsub) + in dispc_plane_state_p_uv_addr()
1985 (y * fb->pitches[1] / fb->format->vsub); in dispc_plane_state_p_uv_addr()
1992 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_setup()
1993 u32 fourcc = state->fb->format->format; in dispc_plane_setup()
1994 u16 cpp = state->fb->format->cpp[0]; in dispc_plane_setup()
1995 u32 fb_width = state->fb->pitches[0] / cpp; in dispc_plane_setup()
2009 (scale.in_w - 1) | ((scale.in_h - 1) << 16)); in dispc_plane_setup()
2020 pixinc(1 + (scale.yinc * fb_width - in dispc_plane_setup()
2024 if (state->fb->format->num_planes == 2) { in dispc_plane_setup()
2025 u16 cpp_uv = state->fb->format->cpp[1]; in dispc_plane_setup()
2026 u32 fb_width_uv = state->fb->pitches[1] / cpp_uv; in dispc_plane_setup()
2039 pixinc(1 + (scale.yinc * fb_width_uv - in dispc_plane_setup()
2046 (state->crtc_w - 1) | in dispc_plane_setup()
2047 ((state->crtc_h - 1) << 16)); in dispc_plane_setup()
2052 /* enable YUV->RGB color conversion */ in dispc_plane_setup()
2061 0xFF & (state->alpha >> 8)); in dispc_plane_setup()
2063 if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) in dispc_plane_setup()
2103 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k2g_plane_init()
2110 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k2g_plane_init()
2116 thr_high = size - 1; in dispc_k2g_plane_init()
2124 dev_dbg(dispc->dev, in dispc_k2g_plane_init()
2126 dispc->feat->vid_name[hw_plane], in dispc_k2g_plane_init()
2140 * Prefetch up to fifo high-threshold value to minimize the in dispc_k2g_plane_init()
2155 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k3_plane_init()
2165 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k3_plane_init()
2171 thr_high = size - 1; in dispc_k3_plane_init()
2179 dev_dbg(dispc->dev, in dispc_k3_plane_init()
2181 dispc->feat->vid_name[hw_plane], in dispc_k3_plane_init()
2202 switch (dispc->feat->subrev) { in dispc_plane_init()
2219 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_vp_init()
2221 /* Enable the gamma Shadow bit-field for all VPs*/ in dispc_vp_init()
2222 for (i = 0; i < dispc->feat->num_vps; i++) in dispc_vp_init()
2232 if (dispc->feat->subrev == DISPC_J721E) { in dispc_initial_config()
2243 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_k2g_vp_write_gamma_table()
2244 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_k2g_vp_write_gamma_table()
2247 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_k2g_vp_write_gamma_table()
2249 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_k2g_vp_write_gamma_table()
2265 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_am65x_vp_write_gamma_table()
2266 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_am65x_vp_write_gamma_table()
2269 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_am65x_vp_write_gamma_table()
2271 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_am65x_vp_write_gamma_table()
2286 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_j721e_vp_write_gamma_table()
2287 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_j721e_vp_write_gamma_table()
2290 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_j721e_vp_write_gamma_table()
2292 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT)) in dispc_j721e_vp_write_gamma_table()
2308 switch (dispc->feat->subrev) { in dispc_vp_write_gamma_table()
2334 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_vp_set_gamma()
2335 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_vp_set_gamma()
2339 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", in dispc_vp_set_gamma()
2342 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) in dispc_vp_set_gamma()
2352 for (i = 0; i < length - 1; ++i) { in dispc_vp_set_gamma()
2353 unsigned int first = i * (hwlen - 1) / (length - 1); in dispc_vp_set_gamma()
2354 unsigned int last = (i + 1) * (hwlen - 1) / (length - 1); in dispc_vp_set_gamma()
2355 unsigned int w = last - first; in dispc_vp_set_gamma()
2363 r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w; in dispc_vp_set_gamma()
2364 g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w; in dispc_vp_set_gamma()
2365 b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w; in dispc_vp_set_gamma()
2367 r >>= 16 - hwbits; in dispc_vp_set_gamma()
2368 g >>= 16 - hwbits; in dispc_vp_set_gamma()
2369 b >>= 16 - hwbits; in dispc_vp_set_gamma()
2386 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x200); in dispc_S31_32_to_s2_8()
2398 cpr->to_regval = dispc_csc_cpr_regval; in dispc_k2g_cpr_from_ctm()
2399 cpr->m[CSC_RR] = dispc_S31_32_to_s2_8(ctm->matrix[0]); in dispc_k2g_cpr_from_ctm()
2400 cpr->m[CSC_RG] = dispc_S31_32_to_s2_8(ctm->matrix[1]); in dispc_k2g_cpr_from_ctm()
2401 cpr->m[CSC_RB] = dispc_S31_32_to_s2_8(ctm->matrix[2]); in dispc_k2g_cpr_from_ctm()
2402 cpr->m[CSC_GR] = dispc_S31_32_to_s2_8(ctm->matrix[3]); in dispc_k2g_cpr_from_ctm()
2403 cpr->m[CSC_GG] = dispc_S31_32_to_s2_8(ctm->matrix[4]); in dispc_k2g_cpr_from_ctm()
2404 cpr->m[CSC_GB] = dispc_S31_32_to_s2_8(ctm->matrix[5]); in dispc_k2g_cpr_from_ctm()
2405 cpr->m[CSC_BR] = dispc_S31_32_to_s2_8(ctm->matrix[6]); in dispc_k2g_cpr_from_ctm()
2406 cpr->m[CSC_BG] = dispc_S31_32_to_s2_8(ctm->matrix[7]); in dispc_k2g_cpr_from_ctm()
2407 cpr->m[CSC_BB] = dispc_S31_32_to_s2_8(ctm->matrix[8]); in dispc_k2g_cpr_from_ctm()
2416 regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); in dispc_k2g_vp_csc_cpr_regval()
2417 regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]); in dispc_k2g_vp_csc_cpr_regval()
2418 regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]); in dispc_k2g_vp_csc_cpr_regval()
2428 /* K2G CPR is packed to three registers. */ in dispc_k2g_vp_write_csc()
2464 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x400); in dispc_S31_32_to_s3_8()
2476 cpr->to_regval = dispc_csc_cpr_regval; in dispc_csc_from_ctm()
2477 cpr->m[CSC_RR] = dispc_S31_32_to_s3_8(ctm->matrix[0]); in dispc_csc_from_ctm()
2478 cpr->m[CSC_RG] = dispc_S31_32_to_s3_8(ctm->matrix[1]); in dispc_csc_from_ctm()
2479 cpr->m[CSC_RB] = dispc_S31_32_to_s3_8(ctm->matrix[2]); in dispc_csc_from_ctm()
2480 cpr->m[CSC_GR] = dispc_S31_32_to_s3_8(ctm->matrix[3]); in dispc_csc_from_ctm()
2481 cpr->m[CSC_GG] = dispc_S31_32_to_s3_8(ctm->matrix[4]); in dispc_csc_from_ctm()
2482 cpr->m[CSC_GB] = dispc_S31_32_to_s3_8(ctm->matrix[5]); in dispc_csc_from_ctm()
2483 cpr->m[CSC_BR] = dispc_S31_32_to_s3_8(ctm->matrix[6]); in dispc_csc_from_ctm()
2484 cpr->m[CSC_BG] = dispc_S31_32_to_s3_8(ctm->matrix[7]); in dispc_csc_from_ctm()
2485 cpr->m[CSC_BB] = dispc_S31_32_to_s3_8(ctm->matrix[8]); in dispc_csc_from_ctm()
2499 csc->to_regval(csc, regval); in dispc_k3_vp_write_csc()
2532 if (!(state->color_mgmt_changed || newmodeset)) in dispc_vp_set_color_mgmt()
2535 if (state->gamma_lut) { in dispc_vp_set_color_mgmt()
2536 lut = (struct drm_color_lut *)state->gamma_lut->data; in dispc_vp_set_color_mgmt()
2537 length = state->gamma_lut->length / sizeof(*lut); in dispc_vp_set_color_mgmt()
2542 if (state->ctm) in dispc_vp_set_color_mgmt()
2543 ctm = (struct drm_color_ctm *)state->ctm->data; in dispc_vp_set_color_mgmt()
2545 if (dispc->feat->subrev == DISPC_K2G) in dispc_vp_set_color_mgmt()
2560 dev_dbg(dispc->dev, "suspend\n"); in dispc_runtime_suspend()
2562 dispc->is_enabled = false; in dispc_runtime_suspend()
2564 clk_disable_unprepare(dispc->fclk); in dispc_runtime_suspend()
2571 dev_dbg(dispc->dev, "resume\n"); in dispc_runtime_resume()
2573 clk_prepare_enable(dispc->fclk); in dispc_runtime_resume()
2576 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); in dispc_runtime_resume()
2578 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", in dispc_runtime_resume()
2581 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2586 if (dispc->feat->subrev == DISPC_AM65X) in dispc_runtime_resume()
2587 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2592 dev_dbg(dispc->dev, "DISPC IDLE %d\n", in dispc_runtime_resume()
2597 dispc->is_enabled = true; in dispc_runtime_resume()
2599 tidss_irq_resume(dispc->tidss); in dispc_runtime_resume()
2606 dev_dbg(tidss->dev, "%s\n", __func__); in dispc_remove()
2608 tidss->dispc = NULL; in dispc_remove()
2618 dev_err(&pdev->dev, "cannot ioremap resource '%s'\n", name); in dispc_iomap_resource()
2630 dispc->oldi_io_ctrl = in dispc_init_am65x_oldi_io_ctrl()
2631 syscon_regmap_lookup_by_phandle(dev->of_node, in dispc_init_am65x_oldi_io_ctrl()
2632 "ti,am65x-oldi-io-ctrl"); in dispc_init_am65x_oldi_io_ctrl()
2633 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { in dispc_init_am65x_oldi_io_ctrl()
2634 dispc->oldi_io_ctrl = NULL; in dispc_init_am65x_oldi_io_ctrl()
2635 } else if (IS_ERR(dispc->oldi_io_ctrl)) { in dispc_init_am65x_oldi_io_ctrl()
2637 __func__, PTR_ERR(dispc->oldi_io_ctrl)); in dispc_init_am65x_oldi_io_ctrl()
2638 return PTR_ERR(dispc->oldi_io_ctrl); in dispc_init_am65x_oldi_io_ctrl()
2651 dispc->errata.i2000 = true; in dispc_init_errata()
2652 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n"); in dispc_init_errata()
2664 ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, in dispc_softreset()
2667 dev_warn(dispc->dev, "failed to reset dispc\n"); in dispc_softreset()
2672 struct device *dev = tidss->dev; in dispc_init()
2681 feat = tidss->feat; in dispc_init()
2683 if (feat->subrev != DISPC_K2G) { in dispc_init()
2686 dev_warn(dev, "cannot set DMA masks to 48-bit\n"); in dispc_init()
2691 return -ENOMEM; in dispc_init()
2693 dispc->tidss = tidss; in dispc_init()
2694 dispc->dev = dev; in dispc_init()
2695 dispc->feat = feat; in dispc_init()
2699 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), in dispc_init()
2700 sizeof(*dispc->fourccs), GFP_KERNEL); in dispc_init()
2701 if (!dispc->fourccs) in dispc_init()
2702 return -ENOMEM; in dispc_init()
2706 if (dispc->errata.i2000 && in dispc_init()
2710 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; in dispc_init()
2713 dispc->num_fourccs = num_fourccs; in dispc_init()
2715 dispc_common_regmap = dispc->feat->common_regs; in dispc_init()
2717 r = dispc_iomap_resource(pdev, dispc->feat->common, in dispc_init()
2718 &dispc->base_common); in dispc_init()
2722 for (i = 0; i < dispc->feat->num_planes; i++) { in dispc_init()
2723 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], in dispc_init()
2724 &dispc->base_vid[i]); in dispc_init()
2729 /* K2G display controller does not support soft reset */ in dispc_init()
2730 if (feat->subrev != DISPC_K2G) in dispc_init()
2733 for (i = 0; i < dispc->feat->num_vps; i++) { in dispc_init()
2734 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; in dispc_init()
2738 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i], in dispc_init()
2739 &dispc->base_ovr[i]); in dispc_init()
2743 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i], in dispc_init()
2744 &dispc->base_vp[i]); in dispc_init()
2748 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); in dispc_init()
2751 dispc->feat->vpclk_name[i], PTR_ERR(clk)); in dispc_init()
2754 dispc->vp_clk[i] = clk; in dispc_init()
2760 return -ENOMEM; in dispc_init()
2761 dispc->vp_data[i].gamma_table = gamma_table; in dispc_init()
2764 if (feat->subrev == DISPC_AM65X) { in dispc_init()
2770 dispc->fclk = devm_clk_get(dev, "fck"); in dispc_init()
2771 if (IS_ERR(dispc->fclk)) { in dispc_init()
2773 __func__, PTR_ERR(dispc->fclk)); in dispc_init()
2774 return PTR_ERR(dispc->fclk); in dispc_init()
2776 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); in dispc_init()
2778 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", in dispc_init()
2779 &dispc->memory_bandwidth_limit); in dispc_init()
2781 tidss->dispc = dispc; in dispc_init()