Lines Matching +full:tegra210 +full:- +full:pmc
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 #include <soc/tegra/pmc.h>
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
510 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
533 * Implementing ->set_parent() here isn't really required because the parent
543 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_set_parent()
567 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_get_parent()
600 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); in tegra_clk_sor_pad_register()
602 return ERR_PTR(-ENOMEM); in tegra_clk_sor_pad_register()
604 pad->sor = sor; in tegra_clk_sor_pad_register()
608 init.parent_names = tegra_clk_sor_pad_parents[sor->index]; in tegra_clk_sor_pad_register()
609 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); in tegra_clk_sor_pad_register()
612 pad->hw.init = &init; in tegra_clk_sor_pad_register()
614 clk = devm_clk_register(sor->dev, &pad->hw); in tegra_clk_sor_pad_register()
621 struct drm_dp_link *link = &sor->link; in tegra_sor_filter_rates()
625 for (i = 0; i < link->num_rates; i++) { in tegra_sor_filter_rates()
626 switch (link->rates[i]) { in tegra_sor_filter_rates()
634 link->rates[i]); in tegra_sor_filter_rates()
635 link->rates[i] = 0; in tegra_sor_filter_rates()
652 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
655 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
656 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); in tegra_sor_power_up_lanes()
658 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
659 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); in tegra_sor_power_up_lanes()
662 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
664 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
667 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
669 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
671 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
689 return -ETIMEDOUT; in tegra_sor_power_up_lanes()
700 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
703 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
721 return -ETIMEDOUT; in tegra_sor_power_down_lanes()
730 /* pre-charge all used lanes */ in tegra_sor_dp_precharge()
731 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
734 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
735 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); in tegra_sor_dp_precharge()
737 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
738 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); in tegra_sor_dp_precharge()
741 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
743 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
746 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
748 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
750 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
754 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
757 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
765 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
767 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
769 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
771 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
776 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
779 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
783 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
790 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
793 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
796 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
798 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
805 const struct tegra_sor_soc *soc = sor->soc; in tegra_sor_dp_link_apply_training()
809 for (value = 0, i = 0; i < link->lanes; i++) { in tegra_sor_dp_link_apply_training()
810 u8 vs = link->train.request.voltage_swing[i]; in tegra_sor_dp_link_apply_training()
811 u8 pe = link->train.request.pre_emphasis[i]; in tegra_sor_dp_link_apply_training()
812 u8 pc = link->train.request.post_cursor[i]; in tegra_sor_dp_link_apply_training()
813 u8 shift = sor->soc->lane_map[i] << 3; in tegra_sor_dp_link_apply_training()
815 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
816 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
817 post_cursor |= soc->post_cursor[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
819 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) in tegra_sor_dp_link_apply_training()
820 tx_pu = sor->soc->tx_pu[pc][vs][pe]; in tegra_sor_dp_link_apply_training()
822 switch (link->train.pattern) { in tegra_sor_dp_link_apply_training()
844 return -EINVAL; in tegra_sor_dp_link_apply_training()
847 if (link->caps.channel_coding) in tegra_sor_dp_link_apply_training()
856 if (link->caps.tps3_supported) in tegra_sor_dp_link_apply_training()
861 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
865 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
879 rate = drm_dp_link_rate_to_bw_code(link->rate); in tegra_sor_dp_link_configure()
880 lanes = link->lanes; in tegra_sor_dp_link_configure()
892 if (link->caps.enhanced_framing) in tegra_sor_dp_link_configure()
900 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
917 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
922 if (link->edp == 0) in tegra_sor_dp_link_configure()
931 dev_err(sor->dev, "failed to power down lanes: %d\n", err); in tegra_sor_dp_link_configure()
935 /* power up and pre-charge lanes */ in tegra_sor_dp_link_configure()
938 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", in tegra_sor_dp_link_configure()
993 return -ETIMEDOUT; in tegra_sor_setup_pwm()
1023 return -ETIMEDOUT; in tegra_sor_attach()
1043 return -ETIMEDOUT; in tegra_sor_wakeup()
1064 return -ETIMEDOUT; in tegra_sor_power_up()
1088 const u64 f = params->precision; in tegra_sor_compute_params()
1091 active_sym = params->ratio * tu_size; in tegra_sor_compute_params()
1093 frac = active_sym - active_count; in tegra_sor_compute_params()
1098 frac = f - frac; in tegra_sor_compute_params()
1121 approx = active_count + (active_frac * (f - 1)) * f; in tegra_sor_compute_params()
1133 error = div_s64(active_sym - approx, tu_size); in tegra_sor_compute_params()
1134 error *= params->num_clocks; in tegra_sor_compute_params()
1136 if (error <= 0 && abs(error) < params->error) { in tegra_sor_compute_params()
1137 params->active_count = div_u64(active_count, f); in tegra_sor_compute_params()
1138 params->active_polarity = active_polarity; in tegra_sor_compute_params()
1139 params->active_frac = active_frac; in tegra_sor_compute_params()
1140 params->error = abs(error); in tegra_sor_compute_params()
1141 params->tu_size = tu_size; in tegra_sor_compute_params()
1155 const u64 f = 100000, link_rate = link->rate * 1000; in tegra_sor_compute_config()
1156 const u64 pclk = mode->clock * 1000; in tegra_sor_compute_config()
1162 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel) in tegra_sor_compute_config()
1163 return -EINVAL; in tegra_sor_compute_config()
1165 input = pclk * config->bits_per_pixel; in tegra_sor_compute_config()
1166 output = link_rate * 8 * link->lanes; in tegra_sor_compute_config()
1169 return -ERANGE; in tegra_sor_compute_config()
1173 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); in tegra_sor_compute_config()
1178 for (i = params.tu_size; i >= 32; i--) in tegra_sor_compute_config()
1183 config->active_polarity = 0; in tegra_sor_compute_config()
1184 config->active_count = params.active_count; in tegra_sor_compute_config()
1187 config->active_count--; in tegra_sor_compute_config()
1189 config->tu_size = params.tu_size; in tegra_sor_compute_config()
1190 config->active_frac = 1; in tegra_sor_compute_config()
1192 config->active_polarity = params.active_polarity; in tegra_sor_compute_config()
1193 config->active_count = params.active_count; in tegra_sor_compute_config()
1194 config->active_frac = params.active_frac; in tegra_sor_compute_config()
1195 config->tu_size = params.tu_size; in tegra_sor_compute_config()
1198 dev_dbg(sor->dev, in tegra_sor_compute_config()
1200 config->active_polarity, config->active_count, in tegra_sor_compute_config()
1201 config->tu_size, config->active_frac); in tegra_sor_compute_config()
1203 watermark = params.ratio * config->tu_size * (f - params.ratio); in tegra_sor_compute_config()
1207 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; in tegra_sor_compute_config()
1208 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * in tegra_sor_compute_config()
1209 (link->lanes * 8); in tegra_sor_compute_config()
1211 if (config->watermark > 30) { in tegra_sor_compute_config()
1212 config->watermark = 30; in tegra_sor_compute_config()
1213 dev_err(sor->dev, in tegra_sor_compute_config()
1215 config->watermark); in tegra_sor_compute_config()
1216 } else if (config->watermark > num_syms_per_line) { in tegra_sor_compute_config()
1217 config->watermark = num_syms_per_line; in tegra_sor_compute_config()
1218 dev_err(sor->dev, "watermark too high, forcing to %u\n", in tegra_sor_compute_config()
1219 config->watermark); in tegra_sor_compute_config()
1223 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; in tegra_sor_compute_config()
1224 config->hblank_symbols = div_u64(num, pclk); in tegra_sor_compute_config()
1226 if (link->caps.enhanced_framing) in tegra_sor_compute_config()
1227 config->hblank_symbols -= 3; in tegra_sor_compute_config()
1229 config->hblank_symbols -= 12 / link->lanes; in tegra_sor_compute_config()
1232 num = (mode->hdisplay - 25) * link_rate; in tegra_sor_compute_config()
1233 config->vblank_symbols = div_u64(num, pclk); in tegra_sor_compute_config()
1234 config->vblank_symbols -= 36 / link->lanes + 4; in tegra_sor_compute_config()
1236 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, in tegra_sor_compute_config()
1237 config->vblank_symbols); in tegra_sor_compute_config()
1249 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
1254 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
1257 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
1260 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
1262 if (config->active_polarity) in tegra_sor_apply_config()
1273 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1278 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1286 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); in tegra_sor_mode_set()
1296 SOR_STATE_ASY_OWNER(dc->pipe + 1); in tegra_sor_mode_set()
1298 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in tegra_sor_mode_set()
1301 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tegra_sor_mode_set()
1304 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in tegra_sor_mode_set()
1307 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tegra_sor_mode_set()
1310 switch (state->bpc) { in tegra_sor_mode_set()
1343 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1344 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1346 /* sync end = sync width - 1 */ in tegra_sor_mode_set()
1347 vse = mode->vsync_end - mode->vsync_start - 1; in tegra_sor_mode_set()
1348 hse = mode->hsync_end - mode->hsync_start - 1; in tegra_sor_mode_set()
1351 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1354 vbe = vse + (mode->vtotal - mode->vsync_end); in tegra_sor_mode_set()
1355 hbe = hse + (mode->htotal - mode->hsync_end); in tegra_sor_mode_set()
1358 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1361 vbs = vbe + mode->vdisplay; in tegra_sor_mode_set()
1362 hbs = hbe + mode->hdisplay; in tegra_sor_mode_set()
1365 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1368 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1390 return -ETIMEDOUT; in tegra_sor_detach()
1415 return -ETIMEDOUT; in tegra_sor_detach()
1441 return -ETIMEDOUT; in tegra_sor_power_down()
1444 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_power_down()
1446 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_power_down()
1450 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1452 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1456 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1458 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1460 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1463 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1484 return -ETIMEDOUT; in tegra_sor_crc_wait()
1489 struct drm_info_node *node = s->private; in tegra_sor_show_crc()
1490 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_crc()
1491 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_crc()
1492 struct drm_device *drm = node->minor->dev; in tegra_sor_show_crc()
1498 if (!crtc || !crtc->state->active) { in tegra_sor_show_crc()
1499 err = -EBUSY; in tegra_sor_show_crc()
1651 struct drm_info_node *node = s->private; in tegra_sor_show_regs()
1652 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_regs()
1653 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_regs()
1654 struct drm_device *drm = node->minor->dev; in tegra_sor_show_regs()
1660 if (!crtc || !crtc->state->active) { in tegra_sor_show_regs()
1661 err = -EBUSY; in tegra_sor_show_regs()
1668 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, in tegra_sor_show_regs()
1686 struct drm_minor *minor = connector->dev->primary; in tegra_sor_late_register()
1687 struct dentry *root = connector->debugfs_entry; in tegra_sor_late_register()
1690 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_sor_late_register()
1692 if (!sor->debugfs_files) in tegra_sor_late_register()
1693 return -ENOMEM; in tegra_sor_late_register()
1696 sor->debugfs_files[i].data = sor; in tegra_sor_late_register()
1698 drm_debugfs_create_files(sor->debugfs_files, count, root, minor); in tegra_sor_late_register()
1709 drm_debugfs_remove_files(sor->debugfs_files, count, in tegra_sor_early_unregister()
1710 connector->dev->primary); in tegra_sor_early_unregister()
1711 kfree(sor->debugfs_files); in tegra_sor_early_unregister()
1712 sor->debugfs_files = NULL; in tegra_sor_early_unregister()
1723 if (connector->state) { in tegra_sor_connector_reset()
1724 __drm_atomic_helper_connector_destroy_state(connector->state); in tegra_sor_connector_reset()
1725 kfree(connector->state); in tegra_sor_connector_reset()
1728 __drm_atomic_helper_connector_reset(connector, &state->base); in tegra_sor_connector_reset()
1737 if (sor->aux) in tegra_sor_connector_detect()
1738 return drm_dp_aux_detect(sor->aux); in tegra_sor_connector_detect()
1746 struct tegra_sor_state *state = to_sor_state(connector->state); in tegra_sor_connector_duplicate_state()
1753 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); in tegra_sor_connector_duplicate_state()
1755 return ©->base; in tegra_sor_connector_duplicate_state()
1775 if (sor->aux) in tegra_sor_connector_get_modes()
1776 drm_dp_aux_enable(sor->aux); in tegra_sor_connector_get_modes()
1780 if (sor->aux) in tegra_sor_connector_get_modes()
1781 drm_dp_aux_disable(sor->aux); in tegra_sor_connector_get_modes()
1805 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); in tegra_sor_encoder_atomic_check()
1806 unsigned long pclk = crtc_state->mode.clock * 1000; in tegra_sor_encoder_atomic_check()
1811 info = &output->connector.display_info; in tegra_sor_encoder_atomic_check()
1818 state->link_speed = 20; in tegra_sor_encoder_atomic_check()
1819 state->pclk = pclk / 2; in tegra_sor_encoder_atomic_check()
1821 state->link_speed = 10; in tegra_sor_encoder_atomic_check()
1822 state->pclk = pclk; in tegra_sor_encoder_atomic_check()
1825 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, in tegra_sor_encoder_atomic_check()
1828 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); in tegra_sor_encoder_atomic_check()
1832 switch (info->bpc) { in tegra_sor_encoder_atomic_check()
1835 state->bpc = info->bpc; in tegra_sor_encoder_atomic_check()
1839 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); in tegra_sor_encoder_atomic_check()
1840 state->bpc = 8; in tegra_sor_encoder_atomic_check()
1852 for (i = size; i > 0; i--) in tegra_sor_hdmi_subpack()
1853 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1880 dev_err(sor->dev, "unsupported infoframe type: %02x\n", in tegra_sor_hdmi_write_infopack()
1893 * - subpack_low: bytes 0 - 3 in tegra_sor_hdmi_write_infopack()
1894 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) in tegra_sor_hdmi_write_infopack()
1897 size_t rem = size - i, num = min_t(size_t, rem, 4); in tegra_sor_hdmi_write_infopack()
1902 num = min_t(size_t, rem - num, 3); in tegra_sor_hdmi_write_infopack()
1926 &sor->output.connector, mode); in tegra_sor_hdmi_setup_avi_infoframe()
1928 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1934 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1951 size_t length = drm_eld_size(sor->output.connector.eld), i; in tegra_sor_write_eld()
1954 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], in tegra_sor_write_eld()
2004 if (sor->format.channels != 2) in tegra_sor_audio_enable()
2026 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2030 frame.channels = sor->format.channels; in tegra_sor_hdmi_enable_audio_infoframe()
2034 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2073 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2086 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2090 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2094 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2124 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
2125 if (frequency <= sor->settings[i].frequency) in tegra_sor_hdmi_find_settings()
2126 return &sor->settings[i]; in tegra_sor_hdmi_find_settings()
2143 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_disable()
2153 if (sor->scdc_enabled) { in tegra_sor_hdmi_scdc_stop()
2154 cancel_delayed_work_sync(&sor->scdc); in tegra_sor_hdmi_scdc_stop()
2171 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_enable()
2182 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_work()
2189 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_work()
2194 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; in tegra_sor_hdmi_scdc_start()
2197 mode = &sor->output.encoder.crtc->state->adjusted_mode; in tegra_sor_hdmi_scdc_start()
2199 if (mode->clock >= 340000 && scdc->supported) { in tegra_sor_hdmi_scdc_start()
2200 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_start()
2202 sor->scdc_enabled = true; in tegra_sor_hdmi_scdc_start()
2209 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_hdmi_disable()
2219 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_hdmi_disable()
2227 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_disable()
2230 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2238 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_hdmi_disable()
2240 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_hdmi_disable()
2242 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_hdmi_disable()
2244 host1x_client_suspend(&sor->client); in tegra_sor_hdmi_disable()
2251 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_hdmi_enable()
2261 state = to_sor_state(output->connector.state); in tegra_sor_hdmi_enable()
2262 mode = &encoder->crtc->state->adjusted_mode; in tegra_sor_hdmi_enable()
2263 pclk = mode->clock * 1000; in tegra_sor_hdmi_enable()
2265 err = host1x_client_resume(&sor->client); in tegra_sor_hdmi_enable()
2267 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_hdmi_enable()
2272 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_hdmi_enable()
2274 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2278 div = clk_get_rate(sor->clk) / 1000000 * 4; in tegra_sor_hdmi_enable()
2280 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_hdmi_enable()
2282 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_hdmi_enable()
2286 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2288 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2294 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2296 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2301 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2303 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2307 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2310 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2314 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2317 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2343 if (mode->clock < 340000) { in tegra_sor_hdmi_enable()
2378 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2386 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2399 err = clk_set_parent(sor->clk_pad, sor->clk_dp); in tegra_sor_hdmi_enable()
2401 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_hdmi_enable()
2408 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_hdmi_enable()
2410 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_hdmi_enable()
2416 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_hdmi_enable()
2418 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_hdmi_enable()
2424 rate = clk_get_rate(sor->clk_parent); in tegra_sor_hdmi_enable()
2426 if (mode->clock >= 340000) in tegra_sor_hdmi_enable()
2431 clk_set_rate(sor->clk, rate); in tegra_sor_hdmi_enable()
2433 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2434 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2437 if (mode->clock < 75000) in tegra_sor_hdmi_enable()
2443 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; in tegra_sor_hdmi_enable()
2449 if (!dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2452 (mode->hsync_end - mode->hsync_start) + in tegra_sor_hdmi_enable()
2453 (mode->htotal - mode->hsync_end) - 10; in tegra_sor_hdmi_enable()
2470 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_enable()
2482 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2484 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2487 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); in tegra_sor_hdmi_enable()
2489 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", in tegra_sor_hdmi_enable()
2490 mode->clock * 1000); in tegra_sor_hdmi_enable()
2494 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2498 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2499 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2500 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2501 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2504 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2507 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2508 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2510 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2512 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2517 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2518 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2519 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2520 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2521 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2523 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2524 settings->drive_current[2] << 16 | in tegra_sor_hdmi_enable()
2525 settings->drive_current[1] << 8 | in tegra_sor_hdmi_enable()
2526 settings->drive_current[0] << 0; in tegra_sor_hdmi_enable()
2529 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2530 settings->preemphasis[2] << 16 | in tegra_sor_hdmi_enable()
2531 settings->preemphasis[1] << 8 | in tegra_sor_hdmi_enable()
2532 settings->preemphasis[0] << 0; in tegra_sor_hdmi_enable()
2535 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2538 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2539 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2541 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2543 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2544 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2547 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2549 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2551 if (!dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2561 switch (state->bpc) { in tegra_sor_hdmi_enable()
2579 WARN(1, "%u bits-per-color not supported\n", state->bpc); in tegra_sor_hdmi_enable()
2589 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2594 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_hdmi_enable()
2597 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2600 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2603 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2606 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2619 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_hdmi_enable()
2624 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_enable()
2627 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2631 if (dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2632 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2635 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2642 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_hdmi_enable()
2657 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_dp_disable()
2662 if (output->panel) in tegra_sor_dp_disable()
2663 drm_panel_disable(output->panel); in tegra_sor_dp_disable()
2669 if (output->connector.status != connector_status_disconnected) { in tegra_sor_dp_disable()
2670 err = drm_dp_link_power_down(sor->aux, &sor->link); in tegra_sor_dp_disable()
2672 dev_err(sor->dev, "failed to power down link: %d\n", in tegra_sor_dp_disable()
2678 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_dp_disable()
2684 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2696 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_disable()
2698 dev_err(sor->dev, "failed to set safe clock: %d\n", err); in tegra_sor_dp_disable()
2702 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_dp_disable()
2704 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_dp_disable()
2706 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_dp_disable()
2708 err = drm_dp_aux_disable(sor->aux); in tegra_sor_dp_disable()
2710 dev_err(sor->dev, "failed disable DPAUX: %d\n", err); in tegra_sor_dp_disable()
2712 if (output->panel) in tegra_sor_dp_disable()
2713 drm_panel_unprepare(output->panel); in tegra_sor_dp_disable()
2715 host1x_client_suspend(&sor->client); in tegra_sor_dp_disable()
2721 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_dp_enable()
2731 state = to_sor_state(output->connector.state); in tegra_sor_dp_enable()
2732 mode = &encoder->crtc->state->adjusted_mode; in tegra_sor_dp_enable()
2733 info = &output->connector.display_info; in tegra_sor_dp_enable()
2735 err = host1x_client_resume(&sor->client); in tegra_sor_dp_enable()
2737 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_dp_enable()
2742 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_enable()
2744 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_dp_enable()
2746 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_dp_enable()
2748 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); in tegra_sor_dp_enable()
2752 err = drm_dp_aux_enable(sor->aux); in tegra_sor_dp_enable()
2754 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); in tegra_sor_dp_enable()
2756 err = drm_dp_link_probe(sor->aux, &sor->link); in tegra_sor_dp_enable()
2758 dev_err(sor->dev, "failed to probe DP link: %d\n", err); in tegra_sor_dp_enable()
2762 err = drm_dp_link_choose(&sor->link, mode, info); in tegra_sor_dp_enable()
2764 dev_err(sor->dev, "failed to choose link: %d\n", err); in tegra_sor_dp_enable()
2766 if (output->panel) in tegra_sor_dp_enable()
2767 drm_panel_prepare(output->panel); in tegra_sor_dp_enable()
2769 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2771 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2781 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2783 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2786 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2790 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2793 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2798 if (output->panel) in tegra_sor_dp_enable()
2809 if (output->panel) in tegra_sor_dp_enable()
2820 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2826 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2830 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2843 err = clk_set_parent(sor->clk_pad, sor->clk_parent); in tegra_sor_dp_enable()
2845 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_dp_enable()
2852 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_dp_enable()
2854 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_dp_enable()
2860 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_dp_enable()
2862 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_dp_enable()
2867 /* use DP-A protocol */ in tegra_sor_dp_enable()
2880 err = drm_dp_link_train(&sor->link); in tegra_sor_dp_enable()
2882 dev_err(sor->dev, "link training failed: %d\n", err); in tegra_sor_dp_enable()
2884 dev_dbg(sor->dev, "link training succeeded\n"); in tegra_sor_dp_enable()
2886 err = drm_dp_link_power_up(sor->aux, &sor->link); in tegra_sor_dp_enable()
2888 dev_err(sor->dev, "failed to power up DP link: %d\n", err); in tegra_sor_dp_enable()
2892 config.bits_per_pixel = state->bpc * 3; in tegra_sor_dp_enable()
2894 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); in tegra_sor_dp_enable()
2896 dev_err(sor->dev, "failed to compute configuration: %d\n", err); in tegra_sor_dp_enable()
2901 if (output->panel) { in tegra_sor_dp_enable()
2910 dev_err(sor->dev, "failed to setup PWM: %d\n", err); in tegra_sor_dp_enable()
2917 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_dp_enable()
2922 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_dp_enable()
2925 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2932 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_dp_enable()
2934 if (output->panel) in tegra_sor_dp_enable()
2935 drm_panel_enable(output->panel); in tegra_sor_dp_enable()
2959 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg); in tegra_sor_enable_regulator()
2966 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_hdmi_probe()
2967 if (IS_ERR(sor->avdd_io_supply)) { in tegra_sor_hdmi_probe()
2968 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", in tegra_sor_hdmi_probe()
2969 PTR_ERR(sor->avdd_io_supply)); in tegra_sor_hdmi_probe()
2970 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2973 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2975 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", in tegra_sor_hdmi_probe()
2980 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_hdmi_probe()
2981 if (IS_ERR(sor->vdd_pll_supply)) { in tegra_sor_hdmi_probe()
2982 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", in tegra_sor_hdmi_probe()
2983 PTR_ERR(sor->vdd_pll_supply)); in tegra_sor_hdmi_probe()
2984 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2987 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2989 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", in tegra_sor_hdmi_probe()
2994 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); in tegra_sor_hdmi_probe()
2995 if (IS_ERR(sor->hdmi_supply)) { in tegra_sor_hdmi_probe()
2996 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", in tegra_sor_hdmi_probe()
2997 PTR_ERR(sor->hdmi_supply)); in tegra_sor_hdmi_probe()
2998 return PTR_ERR(sor->hdmi_supply); in tegra_sor_hdmi_probe()
3001 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply); in tegra_sor_hdmi_probe()
3003 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); in tegra_sor_hdmi_probe()
3007 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); in tegra_sor_hdmi_probe()
3023 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_dp_probe()
3024 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_dp_probe()
3025 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_dp_probe()
3027 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_dp_probe()
3031 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_dp_probe()
3032 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_dp_probe()
3033 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_dp_probe()
3035 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_dp_probe()
3049 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_sor_init()
3056 if (!sor->aux) { in tegra_sor_init()
3057 if (sor->ops == &tegra_sor_hdmi_ops) { in tegra_sor_init()
3061 } else if (sor->soc->supports_lvds) { in tegra_sor_init()
3066 if (sor->output.panel) { in tegra_sor_init()
3076 sor->link.ops = &tegra_sor_dp_link_ops; in tegra_sor_init()
3077 sor->link.aux = sor->aux; in tegra_sor_init()
3080 sor->output.dev = sor->dev; in tegra_sor_init()
3082 drm_connector_init_with_ddc(drm, &sor->output.connector, in tegra_sor_init()
3085 sor->output.ddc); in tegra_sor_init()
3086 drm_connector_helper_add(&sor->output.connector, in tegra_sor_init()
3088 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_sor_init()
3090 drm_simple_encoder_init(drm, &sor->output.encoder, encoder); in tegra_sor_init()
3091 drm_encoder_helper_add(&sor->output.encoder, helpers); in tegra_sor_init()
3093 drm_connector_attach_encoder(&sor->output.connector, in tegra_sor_init()
3094 &sor->output.encoder); in tegra_sor_init()
3095 drm_connector_register(&sor->output.connector); in tegra_sor_init()
3097 err = tegra_output_init(drm, &sor->output); in tegra_sor_init()
3099 dev_err(client->dev, "failed to initialize output: %d\n", err); in tegra_sor_init()
3103 tegra_output_find_possible_crtcs(&sor->output, drm); in tegra_sor_init()
3105 if (sor->aux) { in tegra_sor_init()
3106 err = drm_dp_aux_attach(sor->aux, &sor->output); in tegra_sor_init()
3108 dev_err(sor->dev, "failed to attach DP: %d\n", err); in tegra_sor_init()
3114 * XXX: Remove this reset once proper hand-over from firmware to in tegra_sor_init()
3117 if (sor->rst) { in tegra_sor_init()
3118 err = pm_runtime_resume_and_get(sor->dev); in tegra_sor_init()
3120 dev_err(sor->dev, "failed to get runtime PM: %d\n", err); in tegra_sor_init()
3124 err = reset_control_acquire(sor->rst); in tegra_sor_init()
3126 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", in tegra_sor_init()
3131 err = reset_control_assert(sor->rst); in tegra_sor_init()
3133 dev_err(sor->dev, "failed to assert SOR reset: %d\n", in tegra_sor_init()
3139 err = clk_prepare_enable(sor->clk); in tegra_sor_init()
3141 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_init()
3147 if (sor->rst) { in tegra_sor_init()
3148 err = reset_control_deassert(sor->rst); in tegra_sor_init()
3150 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", in tegra_sor_init()
3152 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3156 reset_control_release(sor->rst); in tegra_sor_init()
3157 pm_runtime_put(sor->dev); in tegra_sor_init()
3160 err = clk_prepare_enable(sor->clk_safe); in tegra_sor_init()
3162 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3166 err = clk_prepare_enable(sor->clk_dp); in tegra_sor_init()
3168 clk_disable_unprepare(sor->clk_safe); in tegra_sor_init()
3169 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3176 if (sor->rst) in tegra_sor_init()
3177 pm_runtime_put(sor->dev); in tegra_sor_init()
3187 tegra_output_exit(&sor->output); in tegra_sor_exit()
3189 if (sor->aux) { in tegra_sor_exit()
3190 err = drm_dp_aux_detach(sor->aux); in tegra_sor_exit()
3192 dev_err(sor->dev, "failed to detach DP: %d\n", err); in tegra_sor_exit()
3197 clk_disable_unprepare(sor->clk_safe); in tegra_sor_exit()
3198 clk_disable_unprepare(sor->clk_dp); in tegra_sor_exit()
3199 clk_disable_unprepare(sor->clk); in tegra_sor_exit()
3207 struct device *dev = client->dev; in tegra_sor_runtime_suspend()
3210 if (sor->rst) { in tegra_sor_runtime_suspend()
3211 err = reset_control_assert(sor->rst); in tegra_sor_runtime_suspend()
3217 reset_control_release(sor->rst); in tegra_sor_runtime_suspend()
3222 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_suspend()
3231 struct device *dev = client->dev; in tegra_sor_runtime_resume()
3240 err = clk_prepare_enable(sor->clk); in tegra_sor_runtime_resume()
3248 if (sor->rst) { in tegra_sor_runtime_resume()
3249 err = reset_control_acquire(sor->rst); in tegra_sor_runtime_resume()
3255 err = reset_control_deassert(sor->rst); in tegra_sor_runtime_resume()
3265 reset_control_release(sor->rst); in tegra_sor_runtime_resume()
3267 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_resume()
3637 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3638 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3639 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3640 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3641 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3642 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3649 struct device_node *np = sor->dev->of_node; in tegra_sor_parse_dt()
3655 if (sor->soc->has_nvdisplay) { in tegra_sor_parse_dt()
3660 sor->index = value; in tegra_sor_parse_dt()
3663 * override the default that we already set for Tegra210 and in tegra_sor_parse_dt()
3666 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; in tegra_sor_parse_dt()
3668 if (!sor->soc->supports_audio) in tegra_sor_parse_dt()
3669 sor->index = 0; in tegra_sor_parse_dt()
3671 sor->index = 1; in tegra_sor_parse_dt()
3674 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); in tegra_sor_parse_dt()
3676 /* fall back to default per-SoC XBAR configuration */ in tegra_sor_parse_dt()
3678 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; in tegra_sor_parse_dt()
3682 sor->xbar_cfg[i] = xbar_cfg[i]; in tegra_sor_parse_dt()
3704 tegra_hda_parse_format(format, &sor->format); in tegra_sor_irq()
3706 if (sor->ops->audio_enable) in tegra_sor_irq()
3707 sor->ops->audio_enable(sor); in tegra_sor_irq()
3709 if (sor->ops->audio_disable) in tegra_sor_irq()
3710 sor->ops->audio_disable(sor); in tegra_sor_irq()
3724 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); in tegra_sor_probe()
3726 return -ENOMEM; in tegra_sor_probe()
3728 sor->soc = of_device_get_match_data(&pdev->dev); in tegra_sor_probe()
3729 sor->output.dev = sor->dev = &pdev->dev; in tegra_sor_probe()
3731 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, in tegra_sor_probe()
3732 sor->soc->num_settings * in tegra_sor_probe()
3733 sizeof(*sor->settings), in tegra_sor_probe()
3735 if (!sor->settings) in tegra_sor_probe()
3736 return -ENOMEM; in tegra_sor_probe()
3738 sor->num_settings = sor->soc->num_settings; in tegra_sor_probe()
3740 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); in tegra_sor_probe()
3742 sor->aux = drm_dp_aux_find_by_of_node(np); in tegra_sor_probe()
3745 if (!sor->aux) in tegra_sor_probe()
3746 return -EPROBE_DEFER; in tegra_sor_probe()
3748 if (get_device(sor->aux->dev)) in tegra_sor_probe()
3749 sor->output.ddc = &sor->aux->ddc; in tegra_sor_probe()
3752 if (!sor->aux) { in tegra_sor_probe()
3753 if (sor->soc->supports_hdmi) { in tegra_sor_probe()
3754 sor->ops = &tegra_sor_hdmi_ops; in tegra_sor_probe()
3755 sor->pad = TEGRA_IO_PAD_HDMI; in tegra_sor_probe()
3756 } else if (sor->soc->supports_lvds) { in tegra_sor_probe()
3757 dev_err(&pdev->dev, "LVDS not supported yet\n"); in tegra_sor_probe()
3758 return -ENODEV; in tegra_sor_probe()
3760 dev_err(&pdev->dev, "unknown (non-DP) support\n"); in tegra_sor_probe()
3761 return -ENODEV; in tegra_sor_probe()
3764 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0); in tegra_sor_probe()
3771 sor->ops = &tegra_sor_dp_ops; in tegra_sor_probe()
3772 sor->pad = TEGRA_IO_PAD_LVDS; in tegra_sor_probe()
3779 err = tegra_output_probe(&sor->output); in tegra_sor_probe()
3781 dev_err_probe(&pdev->dev, err, "failed to probe output\n"); in tegra_sor_probe()
3785 if (sor->ops && sor->ops->probe) { in tegra_sor_probe()
3786 err = sor->ops->probe(sor); in tegra_sor_probe()
3788 dev_err(&pdev->dev, "failed to probe %s: %d\n", in tegra_sor_probe()
3789 sor->ops->name, err); in tegra_sor_probe()
3795 sor->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_sor_probe()
3796 if (IS_ERR(sor->regs)) { in tegra_sor_probe()
3797 err = PTR_ERR(sor->regs); in tegra_sor_probe()
3803 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); in tegra_sor_probe()
3807 sor->irq = err; in tegra_sor_probe()
3809 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, in tegra_sor_probe()
3810 dev_name(sor->dev), sor); in tegra_sor_probe()
3812 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); in tegra_sor_probe()
3816 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); in tegra_sor_probe()
3817 if (IS_ERR(sor->rst)) { in tegra_sor_probe()
3818 err = PTR_ERR(sor->rst); in tegra_sor_probe()
3820 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) { in tegra_sor_probe()
3821 dev_err(&pdev->dev, "failed to get reset control: %d\n", in tegra_sor_probe()
3832 sor->rst = NULL; in tegra_sor_probe()
3835 sor->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sor_probe()
3836 if (IS_ERR(sor->clk)) { in tegra_sor_probe()
3837 err = PTR_ERR(sor->clk); in tegra_sor_probe()
3838 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); in tegra_sor_probe()
3842 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { in tegra_sor_probe()
3843 struct device_node *np = pdev->dev.of_node; in tegra_sor_probe()
3847 * For backwards compatibility with Tegra210 device trees, in tegra_sor_probe()
3851 if (of_property_match_string(np, "clock-names", "out") < 0) in tegra_sor_probe()
3856 sor->clk_out = devm_clk_get(&pdev->dev, name); in tegra_sor_probe()
3857 if (IS_ERR(sor->clk_out)) { in tegra_sor_probe()
3858 err = PTR_ERR(sor->clk_out); in tegra_sor_probe()
3859 dev_err(sor->dev, "failed to get %s clock: %d\n", in tegra_sor_probe()
3865 sor->clk_out = sor->clk; in tegra_sor_probe()
3868 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_sor_probe()
3869 if (IS_ERR(sor->clk_parent)) { in tegra_sor_probe()
3870 err = PTR_ERR(sor->clk_parent); in tegra_sor_probe()
3871 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); in tegra_sor_probe()
3875 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); in tegra_sor_probe()
3876 if (IS_ERR(sor->clk_safe)) { in tegra_sor_probe()
3877 err = PTR_ERR(sor->clk_safe); in tegra_sor_probe()
3878 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); in tegra_sor_probe()
3882 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); in tegra_sor_probe()
3883 if (IS_ERR(sor->clk_dp)) { in tegra_sor_probe()
3884 err = PTR_ERR(sor->clk_dp); in tegra_sor_probe()
3885 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); in tegra_sor_probe()
3893 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); in tegra_sor_probe()
3894 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3895 if (sor->clk_pad != ERR_PTR(-ENOENT)) { in tegra_sor_probe()
3896 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3902 * we're on Tegra210 or earlier and have to provide our own in tegra_sor_probe()
3905 sor->clk_pad = NULL; in tegra_sor_probe()
3913 err = clk_set_parent(sor->clk_out, sor->clk_safe); in tegra_sor_probe()
3915 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); in tegra_sor_probe()
3920 pm_runtime_enable(&pdev->dev); in tegra_sor_probe()
3922 host1x_client_init(&sor->client); in tegra_sor_probe()
3923 sor->client.ops = &sor_client_ops; in tegra_sor_probe()
3924 sor->client.dev = &pdev->dev; in tegra_sor_probe()
3927 * On Tegra210 and earlier, provide our own implementation for the in tegra_sor_probe()
3930 if (!sor->clk_pad) { in tegra_sor_probe()
3933 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout", in tegra_sor_probe()
3934 sor->index); in tegra_sor_probe()
3936 err = -ENOMEM; in tegra_sor_probe()
3940 err = host1x_client_resume(&sor->client); in tegra_sor_probe()
3942 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_probe()
3946 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); in tegra_sor_probe()
3947 host1x_client_suspend(&sor->client); in tegra_sor_probe()
3950 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3951 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3952 dev_err(sor->dev, "failed to register SOR pad clock: %d\n", in tegra_sor_probe()
3957 err = __host1x_client_register(&sor->client); in tegra_sor_probe()
3959 dev_err(&pdev->dev, "failed to register host1x client: %d\n", in tegra_sor_probe()
3967 host1x_client_exit(&sor->client); in tegra_sor_probe()
3968 pm_runtime_disable(&pdev->dev); in tegra_sor_probe()
3970 if (sor->aux) in tegra_sor_probe()
3971 sor->output.ddc = NULL; in tegra_sor_probe()
3973 tegra_output_remove(&sor->output); in tegra_sor_probe()
3975 if (sor->aux) in tegra_sor_probe()
3976 put_device(sor->aux->dev); in tegra_sor_probe()
3986 err = host1x_client_unregister(&sor->client); in tegra_sor_remove()
3988 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", in tegra_sor_remove()
3993 pm_runtime_disable(&pdev->dev); in tegra_sor_remove()
3995 if (sor->aux) { in tegra_sor_remove()
3996 put_device(sor->aux->dev); in tegra_sor_remove()
3997 sor->output.ddc = NULL; in tegra_sor_remove()
4000 tegra_output_remove(&sor->output); in tegra_sor_remove()
4010 err = tegra_output_suspend(&sor->output); in tegra_sor_suspend()
4016 if (sor->hdmi_supply) { in tegra_sor_suspend()
4017 err = regulator_disable(sor->hdmi_supply); in tegra_sor_suspend()
4019 tegra_output_resume(&sor->output); in tegra_sor_suspend()
4032 if (sor->hdmi_supply) { in tegra_sor_resume()
4033 err = regulator_enable(sor->hdmi_supply); in tegra_sor_resume()
4038 err = tegra_output_resume(&sor->output); in tegra_sor_resume()
4042 if (sor->hdmi_supply) in tegra_sor_resume()
4043 regulator_disable(sor->hdmi_supply); in tegra_sor_resume()
4057 .name = "tegra-sor",