Lines Matching full:sor
31 #include "sor.h"
399 int (*probe)(struct tegra_sor *sor);
400 void (*audio_enable)(struct tegra_sor *sor);
401 void (*audio_disable)(struct tegra_sor *sor);
484 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) in tegra_sor_readl() argument
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
500 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) in tegra_sor_set_parent_clock() argument
504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
510 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
519 struct tegra_sor *sor; member
543 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_set_parent() local
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
559 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
567 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_get_parent() local
571 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
593 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, in tegra_clk_sor_pad_register() argument
600 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); in tegra_clk_sor_pad_register()
604 pad->sor = sor; in tegra_clk_sor_pad_register()
608 init.parent_names = tegra_clk_sor_pad_parents[sor->index]; in tegra_clk_sor_pad_register()
609 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); in tegra_clk_sor_pad_register()
614 clk = devm_clk_register(sor->dev, &pad->hw); in tegra_clk_sor_pad_register()
619 static void tegra_sor_filter_rates(struct tegra_sor *sor) in tegra_sor_filter_rates() argument
621 struct drm_dp_link *link = &sor->link; in tegra_sor_filter_rates()
643 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) in tegra_sor_power_up_lanes() argument
652 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
655 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
656 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); in tegra_sor_power_up_lanes()
658 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
659 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); in tegra_sor_power_up_lanes()
662 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
664 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
667 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
669 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
671 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
676 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
681 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
694 static int tegra_sor_power_down_lanes(struct tegra_sor *sor) in tegra_sor_power_down_lanes() argument
700 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
703 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
708 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
713 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
726 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) in tegra_sor_dp_precharge() argument
731 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
734 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
735 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); in tegra_sor_dp_precharge()
737 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
738 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); in tegra_sor_dp_precharge()
741 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
743 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
746 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
748 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
750 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
754 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
757 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
760 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) in tegra_sor_dp_term_calibrate() argument
765 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
767 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
769 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
771 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
776 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
779 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
783 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
790 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
793 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
796 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
798 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
803 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); in tegra_sor_dp_link_apply_training() local
805 const struct tegra_sor_soc *soc = sor->soc; in tegra_sor_dp_link_apply_training()
813 u8 shift = sor->soc->lane_map[i] << 3; in tegra_sor_dp_link_apply_training()
819 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) in tegra_sor_dp_link_apply_training()
820 tx_pu = sor->soc->tx_pu[pc][vs][pe]; in tegra_sor_dp_link_apply_training()
853 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_link_apply_training()
854 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_link_apply_training()
857 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_link_apply_training()
859 tegra_sor_writel(sor, pattern, SOR_DP_TPG); in tegra_sor_dp_link_apply_training()
861 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
865 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
874 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); in tegra_sor_dp_link_configure() local
883 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
886 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
888 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
895 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
900 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
917 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
920 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
927 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
929 err = tegra_sor_power_down_lanes(sor); in tegra_sor_dp_link_configure()
931 dev_err(sor->dev, "failed to power down lanes: %d\n", err); in tegra_sor_dp_link_configure()
936 err = tegra_sor_power_up_lanes(sor, lanes); in tegra_sor_dp_link_configure()
938 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", in tegra_sor_dp_link_configure()
943 tegra_sor_dp_precharge(sor, lanes); in tegra_sor_dp_link_configure()
953 static void tegra_sor_super_update(struct tegra_sor *sor) in tegra_sor_super_update() argument
955 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
956 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); in tegra_sor_super_update()
957 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
960 static void tegra_sor_update(struct tegra_sor *sor) in tegra_sor_update() argument
962 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
963 tegra_sor_writel(sor, 1, SOR_STATE0); in tegra_sor_update()
964 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
967 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_setup_pwm() argument
971 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
974 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
976 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
981 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
986 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
996 static int tegra_sor_attach(struct tegra_sor *sor) in tegra_sor_attach() argument
1001 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1004 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1005 tegra_sor_super_update(sor); in tegra_sor_attach()
1008 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1010 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1011 tegra_sor_super_update(sor); in tegra_sor_attach()
1016 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
1026 static int tegra_sor_wakeup(struct tegra_sor *sor) in tegra_sor_wakeup() argument
1034 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
1046 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_power_up() argument
1050 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1052 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
1057 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1082 static int tegra_sor_compute_params(struct tegra_sor *sor, in tegra_sor_compute_params() argument
1150 static int tegra_sor_compute_config(struct tegra_sor *sor, in tegra_sor_compute_config() argument
1179 if (tegra_sor_compute_params(sor, ¶ms, i)) in tegra_sor_compute_config()
1198 dev_dbg(sor->dev, in tegra_sor_compute_config()
1213 dev_err(sor->dev, in tegra_sor_compute_config()
1218 dev_err(sor->dev, "watermark too high, forcing to %u\n", in tegra_sor_compute_config()
1236 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, in tegra_sor_compute_config()
1242 static void tegra_sor_apply_config(struct tegra_sor *sor, in tegra_sor_apply_config() argument
1247 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1250 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1252 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1269 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1271 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1274 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1276 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1279 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1282 static void tegra_sor_mode_set(struct tegra_sor *sor, in tegra_sor_mode_set() argument
1286 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); in tegra_sor_mode_set()
1290 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1336 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1344 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1351 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1358 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1365 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1368 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1371 static int tegra_sor_detach(struct tegra_sor *sor) in tegra_sor_detach() argument
1376 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1378 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1379 tegra_sor_super_update(sor); in tegra_sor_detach()
1384 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1393 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1395 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1396 tegra_sor_super_update(sor); in tegra_sor_detach()
1399 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1401 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1402 tegra_sor_super_update(sor); in tegra_sor_detach()
1407 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1420 static int tegra_sor_power_down(struct tegra_sor *sor) in tegra_sor_power_down() argument
1425 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1428 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1433 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1444 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_power_down()
1446 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_power_down()
1450 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1452 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1456 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1458 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1460 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1463 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1470 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_crc_wait() argument
1477 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1490 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_crc() local
1491 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_crc()
1503 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1505 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1507 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1509 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1511 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1513 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1515 err = tegra_sor_crc_wait(sor, 100); in tegra_sor_show_crc()
1519 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); in tegra_sor_show_crc()
1520 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1652 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_regs() local
1653 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_regs()
1669 offset, tegra_sor_readl(sor, offset)); in tegra_sor_show_regs()
1688 struct tegra_sor *sor = to_sor(output); in tegra_sor_late_register() local
1690 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_sor_late_register()
1692 if (!sor->debugfs_files) in tegra_sor_late_register()
1696 sor->debugfs_files[i].data = sor; in tegra_sor_late_register()
1698 drm_debugfs_create_files(sor->debugfs_files, count, root, minor); in tegra_sor_late_register()
1707 struct tegra_sor *sor = to_sor(output); in tegra_sor_early_unregister() local
1709 drm_debugfs_remove_files(sor->debugfs_files, count, in tegra_sor_early_unregister()
1711 kfree(sor->debugfs_files); in tegra_sor_early_unregister()
1712 sor->debugfs_files = NULL; in tegra_sor_early_unregister()
1735 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_detect() local
1737 if (sor->aux) in tegra_sor_connector_detect()
1738 return drm_dp_aux_detect(sor->aux); in tegra_sor_connector_detect()
1772 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_get_modes() local
1775 if (sor->aux) in tegra_sor_connector_get_modes()
1776 drm_dp_aux_enable(sor->aux); in tegra_sor_connector_get_modes()
1780 if (sor->aux) in tegra_sor_connector_get_modes()
1781 drm_dp_aux_disable(sor->aux); in tegra_sor_connector_get_modes()
1807 struct tegra_sor *sor = to_sor(output); in tegra_sor_encoder_atomic_check() local
1814 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so in tegra_sor_encoder_atomic_check()
1825 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, in tegra_sor_encoder_atomic_check()
1858 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, in tegra_sor_hdmi_write_infopack() argument
1880 dev_err(sor->dev, "unsupported infoframe type: %02x\n", in tegra_sor_hdmi_write_infopack()
1888 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1900 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1905 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1910 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, in tegra_sor_hdmi_setup_avi_infoframe() argument
1919 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1923 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1926 &sor->output.connector, mode); in tegra_sor_hdmi_setup_avi_infoframe()
1928 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1934 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1938 tegra_sor_hdmi_write_infopack(sor, buffer, err); in tegra_sor_hdmi_setup_avi_infoframe()
1941 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1944 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1949 static void tegra_sor_write_eld(struct tegra_sor *sor) in tegra_sor_write_eld() argument
1951 size_t length = drm_eld_size(sor->output.connector.eld), i; in tegra_sor_write_eld()
1954 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], in tegra_sor_write_eld()
1964 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); in tegra_sor_write_eld()
1967 static void tegra_sor_audio_prepare(struct tegra_sor *sor) in tegra_sor_audio_prepare() argument
1977 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_audio_prepare()
1978 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_audio_prepare()
1980 tegra_sor_write_eld(sor); in tegra_sor_audio_prepare()
1983 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
1986 static void tegra_sor_audio_unprepare(struct tegra_sor *sor) in tegra_sor_audio_unprepare() argument
1988 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_unprepare()
1989 tegra_sor_writel(sor, 0, SOR_INT_MASK); in tegra_sor_audio_unprepare()
1990 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); in tegra_sor_audio_unprepare()
1993 static void tegra_sor_audio_enable(struct tegra_sor *sor) in tegra_sor_audio_enable() argument
1997 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2004 if (sor->format.channels != 2) in tegra_sor_audio_enable()
2011 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2014 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); in tegra_sor_audio_enable()
2017 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) in tegra_sor_hdmi_enable_audio_infoframe() argument
2026 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2030 frame.channels = sor->format.channels; in tegra_sor_hdmi_enable_audio_infoframe()
2034 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2038 tegra_sor_hdmi_write_infopack(sor, buffer, err); in tegra_sor_hdmi_enable_audio_infoframe()
2040 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2043 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2048 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) in tegra_sor_hdmi_audio_enable() argument
2052 tegra_sor_audio_enable(sor); in tegra_sor_hdmi_audio_enable()
2054 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); in tegra_sor_hdmi_audio_enable()
2059 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2063 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2067 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2071 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2073 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2074 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2075 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); in tegra_sor_hdmi_audio_enable()
2077 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); in tegra_sor_hdmi_audio_enable()
2078 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); in tegra_sor_hdmi_audio_enable()
2080 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); in tegra_sor_hdmi_audio_enable()
2081 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); in tegra_sor_hdmi_audio_enable()
2083 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); in tegra_sor_hdmi_audio_enable()
2084 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); in tegra_sor_hdmi_audio_enable()
2086 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2087 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2088 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); in tegra_sor_hdmi_audio_enable()
2090 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2091 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2092 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); in tegra_sor_hdmi_audio_enable()
2094 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2095 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2096 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); in tegra_sor_hdmi_audio_enable()
2098 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2100 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2102 tegra_sor_hdmi_enable_audio_infoframe(sor); in tegra_sor_hdmi_audio_enable()
2105 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) in tegra_sor_hdmi_disable_audio_infoframe() argument
2109 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2111 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2114 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) in tegra_sor_hdmi_audio_disable() argument
2116 tegra_sor_hdmi_disable_audio_infoframe(sor); in tegra_sor_hdmi_audio_disable()
2120 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) in tegra_sor_hdmi_find_settings() argument
2124 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
2125 if (frequency <= sor->settings[i].frequency) in tegra_sor_hdmi_find_settings()
2126 return &sor->settings[i]; in tegra_sor_hdmi_find_settings()
2131 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) in tegra_sor_hdmi_disable_scrambling() argument
2135 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2138 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2141 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_disable() argument
2143 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_disable()
2148 tegra_sor_hdmi_disable_scrambling(sor); in tegra_sor_hdmi_scdc_disable()
2151 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_stop() argument
2153 if (sor->scdc_enabled) { in tegra_sor_hdmi_scdc_stop()
2154 cancel_delayed_work_sync(&sor->scdc); in tegra_sor_hdmi_scdc_stop()
2155 tegra_sor_hdmi_scdc_disable(sor); in tegra_sor_hdmi_scdc_stop()
2159 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) in tegra_sor_hdmi_enable_scrambling() argument
2163 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2166 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2169 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_enable() argument
2171 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_enable()
2176 tegra_sor_hdmi_enable_scrambling(sor); in tegra_sor_hdmi_scdc_enable()
2181 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); in tegra_sor_hdmi_scdc_work() local
2182 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_work()
2186 tegra_sor_hdmi_scdc_enable(sor); in tegra_sor_hdmi_scdc_work()
2189 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_work()
2192 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_start() argument
2194 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; in tegra_sor_hdmi_scdc_start()
2197 mode = &sor->output.encoder.crtc->state->adjusted_mode; in tegra_sor_hdmi_scdc_start()
2200 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_start()
2201 tegra_sor_hdmi_scdc_enable(sor); in tegra_sor_hdmi_scdc_start()
2202 sor->scdc_enabled = true; in tegra_sor_hdmi_scdc_start()
2210 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_disable() local
2214 tegra_sor_audio_unprepare(sor); in tegra_sor_hdmi_disable()
2215 tegra_sor_hdmi_scdc_stop(sor); in tegra_sor_hdmi_disable()
2217 err = tegra_sor_detach(sor); in tegra_sor_hdmi_disable()
2219 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_hdmi_disable()
2221 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_hdmi_disable()
2222 tegra_sor_update(sor); in tegra_sor_hdmi_disable()
2224 /* disable display to SOR clock */ in tegra_sor_hdmi_disable()
2227 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_disable()
2230 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2236 err = tegra_sor_power_down(sor); in tegra_sor_hdmi_disable()
2238 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_hdmi_disable()
2240 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_hdmi_disable()
2242 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_hdmi_disable()
2244 host1x_client_suspend(&sor->client); in tegra_sor_hdmi_disable()
2253 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_enable() local
2265 err = host1x_client_resume(&sor->client); in tegra_sor_hdmi_enable()
2267 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_hdmi_enable()
2272 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_hdmi_enable()
2274 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2278 div = clk_get_rate(sor->clk) / 1000000 * 4; in tegra_sor_hdmi_enable()
2280 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_hdmi_enable()
2282 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_hdmi_enable()
2286 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2288 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2294 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2296 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2301 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2303 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2307 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2310 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2314 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2317 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2320 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2329 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2332 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2339 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2352 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2354 /* SOR pad PLL stabilization time */ in tegra_sor_hdmi_enable()
2357 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2360 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2362 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2367 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2371 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2376 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2378 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2381 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2386 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2389 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_hdmi_enable()
2390 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2399 err = clk_set_parent(sor->clk_pad, sor->clk_dp); in tegra_sor_hdmi_enable()
2401 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_hdmi_enable()
2407 /* switch the SOR clock to the pad clock */ in tegra_sor_hdmi_enable()
2408 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_hdmi_enable()
2410 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_hdmi_enable()
2416 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_hdmi_enable()
2418 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_hdmi_enable()
2424 rate = clk_get_rate(sor->clk_parent); in tegra_sor_hdmi_enable()
2431 clk_set_rate(sor->clk, rate); in tegra_sor_hdmi_enable()
2433 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2440 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2447 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2468 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); in tegra_sor_hdmi_enable()
2470 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_enable()
2473 tegra_sor_hdmi_disable_audio_infoframe(sor); in tegra_sor_hdmi_enable()
2476 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2479 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2482 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2484 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2487 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); in tegra_sor_hdmi_enable()
2489 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", in tegra_sor_hdmi_enable()
2494 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2501 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2504 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2510 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2512 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2521 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2527 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2533 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2535 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2539 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2541 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2544 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2547 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2549 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2587 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2590 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2592 err = tegra_sor_power_up(sor, 250); in tegra_sor_hdmi_enable()
2594 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_hdmi_enable()
2597 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2600 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2603 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2606 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2608 tegra_sor_mode_set(sor, mode, state); in tegra_sor_hdmi_enable()
2610 tegra_sor_update(sor); in tegra_sor_hdmi_enable()
2612 /* program preamble timing in SOR (XXX) */ in tegra_sor_hdmi_enable()
2613 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2615 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2617 err = tegra_sor_attach(sor); in tegra_sor_hdmi_enable()
2619 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_hdmi_enable()
2621 /* enable display to SOR clock and generate HDMI preamble */ in tegra_sor_hdmi_enable()
2624 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_enable()
2627 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2632 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2635 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2640 err = tegra_sor_wakeup(sor); in tegra_sor_hdmi_enable()
2642 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_hdmi_enable()
2644 tegra_sor_hdmi_scdc_start(sor); in tegra_sor_hdmi_enable()
2645 tegra_sor_audio_prepare(sor); in tegra_sor_hdmi_enable()
2658 struct tegra_sor *sor = to_sor(output); in tegra_sor_dp_disable() local
2670 err = drm_dp_link_power_down(sor->aux, &sor->link); in tegra_sor_dp_disable()
2672 dev_err(sor->dev, "failed to power down link: %d\n", in tegra_sor_dp_disable()
2676 err = tegra_sor_detach(sor); in tegra_sor_dp_disable()
2678 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_dp_disable()
2680 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_dp_disable()
2681 tegra_sor_update(sor); in tegra_sor_dp_disable()
2684 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2688 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_disable()
2692 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_disable()
2693 tegra_sor_update(sor); in tegra_sor_dp_disable()
2696 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_disable()
2698 dev_err(sor->dev, "failed to set safe clock: %d\n", err); in tegra_sor_dp_disable()
2700 err = tegra_sor_power_down(sor); in tegra_sor_dp_disable()
2702 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_dp_disable()
2704 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_dp_disable()
2706 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_dp_disable()
2708 err = drm_dp_aux_disable(sor->aux); in tegra_sor_dp_disable()
2710 dev_err(sor->dev, "failed disable DPAUX: %d\n", err); in tegra_sor_dp_disable()
2715 host1x_client_suspend(&sor->client); in tegra_sor_dp_disable()
2722 struct tegra_sor *sor = to_sor(output); in tegra_sor_dp_enable() local
2735 err = host1x_client_resume(&sor->client); in tegra_sor_dp_enable()
2737 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_dp_enable()
2742 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_enable()
2744 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_dp_enable()
2746 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_dp_enable()
2748 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); in tegra_sor_dp_enable()
2752 err = drm_dp_aux_enable(sor->aux); in tegra_sor_dp_enable()
2754 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); in tegra_sor_dp_enable()
2756 err = drm_dp_link_probe(sor->aux, &sor->link); in tegra_sor_dp_enable()
2758 dev_err(sor->dev, "failed to probe DP link: %d\n", err); in tegra_sor_dp_enable()
2760 tegra_sor_filter_rates(sor); in tegra_sor_dp_enable()
2762 err = drm_dp_link_choose(&sor->link, mode, info); in tegra_sor_dp_enable()
2764 dev_err(sor->dev, "failed to choose link: %d\n", err); in tegra_sor_dp_enable()
2769 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2771 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2781 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2783 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2786 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2790 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2793 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2795 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2803 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2807 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2815 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2818 tegra_sor_writel(sor, 0, SOR_LVDS); in tegra_sor_dp_enable()
2820 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2826 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2830 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2833 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_dp_enable()
2834 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_dp_enable()
2843 err = clk_set_parent(sor->clk_pad, sor->clk_parent); in tegra_sor_dp_enable()
2845 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_dp_enable()
2851 /* switch the SOR clock to the pad clock */ in tegra_sor_dp_enable()
2852 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_dp_enable()
2854 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_dp_enable()
2860 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_dp_enable()
2862 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_dp_enable()
2868 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_enable()
2871 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_enable()
2874 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2876 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2878 tegra_sor_dp_term_calibrate(sor); in tegra_sor_dp_enable()
2880 err = drm_dp_link_train(&sor->link); in tegra_sor_dp_enable()
2882 dev_err(sor->dev, "link training failed: %d\n", err); in tegra_sor_dp_enable()
2884 dev_dbg(sor->dev, "link training succeeded\n"); in tegra_sor_dp_enable()
2886 err = drm_dp_link_power_up(sor->aux, &sor->link); in tegra_sor_dp_enable()
2888 dev_err(sor->dev, "failed to power up DP link: %d\n", err); in tegra_sor_dp_enable()
2894 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); in tegra_sor_dp_enable()
2896 dev_err(sor->dev, "failed to compute configuration: %d\n", err); in tegra_sor_dp_enable()
2898 tegra_sor_apply_config(sor, &config); in tegra_sor_dp_enable()
2899 tegra_sor_mode_set(sor, mode, state); in tegra_sor_dp_enable()
2905 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_dp_enable()
2908 err = tegra_sor_setup_pwm(sor, 250); in tegra_sor_dp_enable()
2910 dev_err(sor->dev, "failed to setup PWM: %d\n", err); in tegra_sor_dp_enable()
2913 tegra_sor_update(sor); in tegra_sor_dp_enable()
2915 err = tegra_sor_power_up(sor, 250); in tegra_sor_dp_enable()
2917 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_dp_enable()
2920 err = tegra_sor_attach(sor); in tegra_sor_dp_enable()
2922 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_dp_enable()
2925 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2930 err = tegra_sor_wakeup(sor); in tegra_sor_dp_enable()
2932 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_dp_enable()
2951 static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg) in tegra_sor_enable_regulator() argument
2959 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg); in tegra_sor_enable_regulator()
2962 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) in tegra_sor_hdmi_probe() argument
2966 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_hdmi_probe()
2967 if (IS_ERR(sor->avdd_io_supply)) { in tegra_sor_hdmi_probe()
2968 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", in tegra_sor_hdmi_probe()
2969 PTR_ERR(sor->avdd_io_supply)); in tegra_sor_hdmi_probe()
2970 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2973 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2975 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", in tegra_sor_hdmi_probe()
2980 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_hdmi_probe()
2981 if (IS_ERR(sor->vdd_pll_supply)) { in tegra_sor_hdmi_probe()
2982 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", in tegra_sor_hdmi_probe()
2983 PTR_ERR(sor->vdd_pll_supply)); in tegra_sor_hdmi_probe()
2984 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2987 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2989 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", in tegra_sor_hdmi_probe()
2994 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); in tegra_sor_hdmi_probe()
2995 if (IS_ERR(sor->hdmi_supply)) { in tegra_sor_hdmi_probe()
2996 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", in tegra_sor_hdmi_probe()
2997 PTR_ERR(sor->hdmi_supply)); in tegra_sor_hdmi_probe()
2998 return PTR_ERR(sor->hdmi_supply); in tegra_sor_hdmi_probe()
3001 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply); in tegra_sor_hdmi_probe()
3003 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); in tegra_sor_hdmi_probe()
3007 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); in tegra_sor_hdmi_probe()
3019 static int tegra_sor_dp_probe(struct tegra_sor *sor) in tegra_sor_dp_probe() argument
3023 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_dp_probe()
3024 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_dp_probe()
3025 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_dp_probe()
3027 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_dp_probe()
3031 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_dp_probe()
3032 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_dp_probe()
3033 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_dp_probe()
3035 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_dp_probe()
3051 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_init() local
3056 if (!sor->aux) { in tegra_sor_init()
3057 if (sor->ops == &tegra_sor_hdmi_ops) { in tegra_sor_init()
3061 } else if (sor->soc->supports_lvds) { in tegra_sor_init()
3066 if (sor->output.panel) { in tegra_sor_init()
3076 sor->link.ops = &tegra_sor_dp_link_ops; in tegra_sor_init()
3077 sor->link.aux = sor->aux; in tegra_sor_init()
3080 sor->output.dev = sor->dev; in tegra_sor_init()
3082 drm_connector_init_with_ddc(drm, &sor->output.connector, in tegra_sor_init()
3085 sor->output.ddc); in tegra_sor_init()
3086 drm_connector_helper_add(&sor->output.connector, in tegra_sor_init()
3088 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_sor_init()
3090 drm_simple_encoder_init(drm, &sor->output.encoder, encoder); in tegra_sor_init()
3091 drm_encoder_helper_add(&sor->output.encoder, helpers); in tegra_sor_init()
3093 drm_connector_attach_encoder(&sor->output.connector, in tegra_sor_init()
3094 &sor->output.encoder); in tegra_sor_init()
3095 drm_connector_register(&sor->output.connector); in tegra_sor_init()
3097 err = tegra_output_init(drm, &sor->output); in tegra_sor_init()
3103 tegra_output_find_possible_crtcs(&sor->output, drm); in tegra_sor_init()
3105 if (sor->aux) { in tegra_sor_init()
3106 err = drm_dp_aux_attach(sor->aux, &sor->output); in tegra_sor_init()
3108 dev_err(sor->dev, "failed to attach DP: %d\n", err); in tegra_sor_init()
3117 if (sor->rst) { in tegra_sor_init()
3118 err = pm_runtime_resume_and_get(sor->dev); in tegra_sor_init()
3120 dev_err(sor->dev, "failed to get runtime PM: %d\n", err); in tegra_sor_init()
3124 err = reset_control_acquire(sor->rst); in tegra_sor_init()
3126 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", in tegra_sor_init()
3131 err = reset_control_assert(sor->rst); in tegra_sor_init()
3133 dev_err(sor->dev, "failed to assert SOR reset: %d\n", in tegra_sor_init()
3139 err = clk_prepare_enable(sor->clk); in tegra_sor_init()
3141 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_init()
3147 if (sor->rst) { in tegra_sor_init()
3148 err = reset_control_deassert(sor->rst); in tegra_sor_init()
3150 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", in tegra_sor_init()
3152 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3156 reset_control_release(sor->rst); in tegra_sor_init()
3157 pm_runtime_put(sor->dev); in tegra_sor_init()
3160 err = clk_prepare_enable(sor->clk_safe); in tegra_sor_init()
3162 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3166 err = clk_prepare_enable(sor->clk_dp); in tegra_sor_init()
3168 clk_disable_unprepare(sor->clk_safe); in tegra_sor_init()
3169 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3176 if (sor->rst) in tegra_sor_init()
3177 pm_runtime_put(sor->dev); in tegra_sor_init()
3184 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_exit() local
3187 tegra_output_exit(&sor->output); in tegra_sor_exit()
3189 if (sor->aux) { in tegra_sor_exit()
3190 err = drm_dp_aux_detach(sor->aux); in tegra_sor_exit()
3192 dev_err(sor->dev, "failed to detach DP: %d\n", err); in tegra_sor_exit()
3197 clk_disable_unprepare(sor->clk_safe); in tegra_sor_exit()
3198 clk_disable_unprepare(sor->clk_dp); in tegra_sor_exit()
3199 clk_disable_unprepare(sor->clk); in tegra_sor_exit()
3206 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_runtime_suspend() local
3210 if (sor->rst) { in tegra_sor_runtime_suspend()
3211 err = reset_control_assert(sor->rst); in tegra_sor_runtime_suspend()
3217 reset_control_release(sor->rst); in tegra_sor_runtime_suspend()
3222 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_suspend()
3230 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_runtime_resume() local
3240 err = clk_prepare_enable(sor->clk); in tegra_sor_runtime_resume()
3248 if (sor->rst) { in tegra_sor_runtime_resume()
3249 err = reset_control_acquire(sor->rst); in tegra_sor_runtime_resume()
3255 err = reset_control_deassert(sor->rst); in tegra_sor_runtime_resume()
3265 reset_control_release(sor->rst); in tegra_sor_runtime_resume()
3267 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_resume()
3637 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3638 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3640 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3641 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3642 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3647 static int tegra_sor_parse_dt(struct tegra_sor *sor) in tegra_sor_parse_dt() argument
3649 struct device_node *np = sor->dev->of_node; in tegra_sor_parse_dt()
3655 if (sor->soc->has_nvdisplay) { in tegra_sor_parse_dt()
3660 sor->index = value; in tegra_sor_parse_dt()
3666 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; in tegra_sor_parse_dt()
3668 if (!sor->soc->supports_audio) in tegra_sor_parse_dt()
3669 sor->index = 0; in tegra_sor_parse_dt()
3671 sor->index = 1; in tegra_sor_parse_dt()
3678 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; in tegra_sor_parse_dt()
3680 /* copy cells to SOR XBAR configuration */ in tegra_sor_parse_dt()
3682 sor->xbar_cfg[i] = xbar_cfg[i]; in tegra_sor_parse_dt()
3690 struct tegra_sor *sor = data; in tegra_sor_irq() local
3693 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3694 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()
3697 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()
3704 tegra_hda_parse_format(format, &sor->format); in tegra_sor_irq()
3706 if (sor->ops->audio_enable) in tegra_sor_irq()
3707 sor->ops->audio_enable(sor); in tegra_sor_irq()
3709 if (sor->ops->audio_disable) in tegra_sor_irq()
3710 sor->ops->audio_disable(sor); in tegra_sor_irq()
3720 struct tegra_sor *sor; in tegra_sor_probe() local
3724 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); in tegra_sor_probe()
3725 if (!sor) in tegra_sor_probe()
3728 sor->soc = of_device_get_match_data(&pdev->dev); in tegra_sor_probe()
3729 sor->output.dev = sor->dev = &pdev->dev; in tegra_sor_probe()
3731 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, in tegra_sor_probe()
3732 sor->soc->num_settings * in tegra_sor_probe()
3733 sizeof(*sor->settings), in tegra_sor_probe()
3735 if (!sor->settings) in tegra_sor_probe()
3738 sor->num_settings = sor->soc->num_settings; in tegra_sor_probe()
3742 sor->aux = drm_dp_aux_find_by_of_node(np); in tegra_sor_probe()
3745 if (!sor->aux) in tegra_sor_probe()
3748 if (get_device(sor->aux->dev)) in tegra_sor_probe()
3749 sor->output.ddc = &sor->aux->ddc; in tegra_sor_probe()
3752 if (!sor->aux) { in tegra_sor_probe()
3753 if (sor->soc->supports_hdmi) { in tegra_sor_probe()
3754 sor->ops = &tegra_sor_hdmi_ops; in tegra_sor_probe()
3755 sor->pad = TEGRA_IO_PAD_HDMI; in tegra_sor_probe()
3756 } else if (sor->soc->supports_lvds) { in tegra_sor_probe()
3771 sor->ops = &tegra_sor_dp_ops; in tegra_sor_probe()
3772 sor->pad = TEGRA_IO_PAD_LVDS; in tegra_sor_probe()
3775 err = tegra_sor_parse_dt(sor); in tegra_sor_probe()
3779 err = tegra_output_probe(&sor->output); in tegra_sor_probe()
3785 if (sor->ops && sor->ops->probe) { in tegra_sor_probe()
3786 err = sor->ops->probe(sor); in tegra_sor_probe()
3789 sor->ops->name, err); in tegra_sor_probe()
3795 sor->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_sor_probe()
3796 if (IS_ERR(sor->regs)) { in tegra_sor_probe()
3797 err = PTR_ERR(sor->regs); in tegra_sor_probe()
3807 sor->irq = err; in tegra_sor_probe()
3809 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, in tegra_sor_probe()
3810 dev_name(sor->dev), sor); in tegra_sor_probe()
3816 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); in tegra_sor_probe()
3817 if (IS_ERR(sor->rst)) { in tegra_sor_probe()
3818 err = PTR_ERR(sor->rst); in tegra_sor_probe()
3829 * the power domain will have taken care of resetting the SOR in tegra_sor_probe()
3832 sor->rst = NULL; in tegra_sor_probe()
3835 sor->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sor_probe()
3836 if (IS_ERR(sor->clk)) { in tegra_sor_probe()
3837 err = PTR_ERR(sor->clk); in tegra_sor_probe()
3842 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { in tegra_sor_probe()
3856 sor->clk_out = devm_clk_get(&pdev->dev, name); in tegra_sor_probe()
3857 if (IS_ERR(sor->clk_out)) { in tegra_sor_probe()
3858 err = PTR_ERR(sor->clk_out); in tegra_sor_probe()
3859 dev_err(sor->dev, "failed to get %s clock: %d\n", in tegra_sor_probe()
3865 sor->clk_out = sor->clk; in tegra_sor_probe()
3868 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_sor_probe()
3869 if (IS_ERR(sor->clk_parent)) { in tegra_sor_probe()
3870 err = PTR_ERR(sor->clk_parent); in tegra_sor_probe()
3875 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); in tegra_sor_probe()
3876 if (IS_ERR(sor->clk_safe)) { in tegra_sor_probe()
3877 err = PTR_ERR(sor->clk_safe); in tegra_sor_probe()
3882 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); in tegra_sor_probe()
3883 if (IS_ERR(sor->clk_dp)) { in tegra_sor_probe()
3884 err = PTR_ERR(sor->clk_dp); in tegra_sor_probe()
3893 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); in tegra_sor_probe()
3894 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3895 if (sor->clk_pad != ERR_PTR(-ENOENT)) { in tegra_sor_probe()
3896 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3905 sor->clk_pad = NULL; in tegra_sor_probe()
3909 * The bootloader may have set up the SOR such that it's module clock in tegra_sor_probe()
3911 * without properly having set up other bits of the SOR. in tegra_sor_probe()
3913 err = clk_set_parent(sor->clk_out, sor->clk_safe); in tegra_sor_probe()
3919 platform_set_drvdata(pdev, sor); in tegra_sor_probe()
3922 host1x_client_init(&sor->client); in tegra_sor_probe()
3923 sor->client.ops = &sor_client_ops; in tegra_sor_probe()
3924 sor->client.dev = &pdev->dev; in tegra_sor_probe()
3930 if (!sor->clk_pad) { in tegra_sor_probe()
3933 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout", in tegra_sor_probe()
3934 sor->index); in tegra_sor_probe()
3940 err = host1x_client_resume(&sor->client); in tegra_sor_probe()
3942 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_probe()
3946 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); in tegra_sor_probe()
3947 host1x_client_suspend(&sor->client); in tegra_sor_probe()
3950 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3951 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3952 dev_err(sor->dev, "failed to register SOR pad clock: %d\n", in tegra_sor_probe()
3957 err = __host1x_client_register(&sor->client); in tegra_sor_probe()
3967 host1x_client_exit(&sor->client); in tegra_sor_probe()
3970 if (sor->aux) in tegra_sor_probe()
3971 sor->output.ddc = NULL; in tegra_sor_probe()
3973 tegra_output_remove(&sor->output); in tegra_sor_probe()
3975 if (sor->aux) in tegra_sor_probe()
3976 put_device(sor->aux->dev); in tegra_sor_probe()
3983 struct tegra_sor *sor = platform_get_drvdata(pdev); in tegra_sor_remove() local
3986 err = host1x_client_unregister(&sor->client); in tegra_sor_remove()
3995 if (sor->aux) { in tegra_sor_remove()
3996 put_device(sor->aux->dev); in tegra_sor_remove()
3997 sor->output.ddc = NULL; in tegra_sor_remove()
4000 tegra_output_remove(&sor->output); in tegra_sor_remove()
4007 struct tegra_sor *sor = dev_get_drvdata(dev); in tegra_sor_suspend() local
4010 err = tegra_output_suspend(&sor->output); in tegra_sor_suspend()
4016 if (sor->hdmi_supply) { in tegra_sor_suspend()
4017 err = regulator_disable(sor->hdmi_supply); in tegra_sor_suspend()
4019 tegra_output_resume(&sor->output); in tegra_sor_suspend()
4029 struct tegra_sor *sor = dev_get_drvdata(dev); in tegra_sor_resume() local
4032 if (sor->hdmi_supply) { in tegra_sor_resume()
4033 err = regulator_enable(sor->hdmi_supply); in tegra_sor_resume()
4038 err = tegra_output_resume(&sor->output); in tegra_sor_resume()
4042 if (sor->hdmi_supply) in tegra_sor_resume()
4043 regulator_disable(sor->hdmi_supply); in tegra_sor_resume()
4057 .name = "tegra-sor",