Lines Matching full:pll1
41 u32 pll1; member
139 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
154 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
172 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
186 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
200 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
217 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
235 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
254 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
273 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
296 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
314 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
333 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
352 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
836 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); in tegra_hdmi_setup_tmds()