Lines Matching +full:tegra210 +full:- +full:sor
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
27 #include <asm/dma-iommu.h>
79 struct drm_device *drm = old_state->dev;
80 struct tegra_drm *tegra = drm->dev_private;
82 if (tegra->hub) {
111 return -ENOMEM;
113 idr_init_base(&fpriv->legacy_contexts, 1);
114 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1);
115 xa_init(&fpriv->syncpoints);
116 mutex_init(&fpriv->lock);
117 filp->driver_priv = fpriv;
124 context->client->ops->close_channel(context);
125 pm_runtime_put(context->client->base.dev);
137 err = get_user(cmdbuf, &src->cmdbuf.handle);
141 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
145 err = get_user(target, &src->target.handle);
149 err = get_user(dest->target.offset, &src->target.offset);
153 err = get_user(dest->shift, &src->shift);
157 dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
159 dest->cmdbuf.bo = tegra_gem_lookup(file, cmdbuf);
160 if (!dest->cmdbuf.bo)
161 return -ENOENT;
163 dest->target.bo = tegra_gem_lookup(file, target);
164 if (!dest->target.bo)
165 return -ENOENT;
174 struct host1x_client *client = &context->client->base;
175 unsigned int num_cmdbufs = args->num_cmdbufs;
176 unsigned int num_relocs = args->num_relocs;
181 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
188 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
189 user_relocs = u64_to_user_ptr(args->relocs);
190 user_syncpt = u64_to_user_ptr(args->syncpts);
193 if (args->num_syncpts != 1)
194 return -EINVAL;
197 if (args->num_waitchks != 0)
198 return -EINVAL;
200 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
201 args->num_relocs, false);
203 return -ENOMEM;
205 job->num_relocs = args->num_relocs;
206 job->client = client;
207 job->class = client->class;
208 job->serialize = true;
209 job->syncpt_recovery = true;
219 err = -ENOMEM;
233 err = -EFAULT;
242 err = -EINVAL;
248 err = -ENOENT;
254 refs[num_refs++] = &obj->gem;
257 * Gather buffer base address must be 4-bytes aligned,
261 if (offset & 3 || offset > obj->gem.size) {
262 err = -EINVAL;
267 num_cmdbufs--;
272 while (num_relocs--) {
276 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
282 reloc = &job->relocs[num_relocs];
283 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
284 refs[num_refs++] = &obj->gem;
291 if (reloc->cmdbuf.offset & 3 ||
292 reloc->cmdbuf.offset >= obj->gem.size) {
293 err = -EINVAL;
297 obj = host1x_to_tegra_bo(reloc->target.bo);
298 refs[num_refs++] = &obj->gem;
300 if (reloc->target.offset >= obj->gem.size) {
301 err = -EINVAL;
307 err = -EFAULT;
314 err = -ENOENT;
318 job->is_addr_reg = context->client->ops->is_addr_reg;
319 job->is_valid_class = context->client->ops->is_valid_class;
320 job->syncpt_incrs = syncpt.incrs;
321 job->syncpt = sp;
322 job->timeout = 10000;
324 if (args->timeout && args->timeout < 10000)
325 job->timeout = args->timeout;
327 err = host1x_job_pin(job, context->client->base.dev);
337 args->fence = job->syncpt_end;
340 while (num_refs--)
358 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
359 &args->handle);
373 gem = drm_gem_object_lookup(file, args->handle);
375 return -EINVAL;
379 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
389 struct host1x *host = dev_get_drvdata(drm->dev->parent);
393 sp = host1x_syncpt_get_by_id_noref(host, args->id);
395 return -EINVAL;
397 args->value = host1x_syncpt_read_min(sp);
404 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
408 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
410 return -EINVAL;
418 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
422 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
424 return -EINVAL;
426 return host1x_syncpt_wait(sp, args->thresh,
427 msecs_to_jiffies(args->timeout),
428 &args->value);
437 err = pm_runtime_resume_and_get(client->base.dev);
441 err = client->ops->open_channel(client, context);
443 pm_runtime_put(client->base.dev);
447 err = idr_alloc(&fpriv->legacy_contexts, context, 1, 0, GFP_KERNEL);
449 client->ops->close_channel(context);
450 pm_runtime_put(client->base.dev);
454 context->client = client;
455 context->id = err;
463 struct tegra_drm_file *fpriv = file->driver_priv;
464 struct tegra_drm *tegra = drm->dev_private;
468 int err = -ENODEV;
472 return -ENOMEM;
474 mutex_lock(&fpriv->lock);
476 list_for_each_entry(client, &tegra->clients, list)
477 if (client->base.class == args->client) {
482 args->context = context->id;
489 mutex_unlock(&fpriv->lock);
496 struct tegra_drm_file *fpriv = file->driver_priv;
501 mutex_lock(&fpriv->lock);
503 context = idr_find(&fpriv->legacy_contexts, args->context);
505 err = -EINVAL;
509 idr_remove(&fpriv->legacy_contexts, context->id);
513 mutex_unlock(&fpriv->lock);
520 struct tegra_drm_file *fpriv = file->driver_priv;
526 mutex_lock(&fpriv->lock);
528 context = idr_find(&fpriv->legacy_contexts, args->context);
530 err = -ENODEV;
534 if (args->index >= context->client->base.num_syncpts) {
535 err = -EINVAL;
539 syncpt = context->client->base.syncpts[args->index];
540 args->id = host1x_syncpt_id(syncpt);
543 mutex_unlock(&fpriv->lock);
550 struct tegra_drm_file *fpriv = file->driver_priv;
555 mutex_lock(&fpriv->lock);
557 context = idr_find(&fpriv->legacy_contexts, args->context);
559 err = -ENODEV;
563 err = context->client->ops->submit(context, args, drm, file);
566 mutex_unlock(&fpriv->lock);
573 struct tegra_drm_file *fpriv = file->driver_priv;
580 mutex_lock(&fpriv->lock);
582 context = idr_find(&fpriv->legacy_contexts, args->context);
584 err = -ENODEV;
588 if (args->syncpt >= context->client->base.num_syncpts) {
589 err = -EINVAL;
593 syncpt = context->client->base.syncpts[args->syncpt];
597 err = -ENXIO;
601 args->id = host1x_syncpt_base_id(base);
604 mutex_unlock(&fpriv->lock);
617 switch (args->mode) {
621 if (args->value != 0)
622 return -EINVAL;
629 if (args->value != 0)
630 return -EINVAL;
637 if (args->value > 5)
638 return -EINVAL;
640 value = args->value;
644 return -EINVAL;
647 gem = drm_gem_object_lookup(file, args->handle);
649 return -ENOENT;
653 bo->tiling.mode = mode;
654 bo->tiling.value = value;
669 gem = drm_gem_object_lookup(file, args->handle);
671 return -ENOENT;
675 switch (bo->tiling.mode) {
677 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
678 args->value = 0;
682 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
683 args->value = 0;
687 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
688 args->value = bo->tiling.value;
692 err = -EINVAL;
708 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
709 return -EINVAL;
711 gem = drm_gem_object_lookup(file, args->handle);
713 return -ENOENT;
716 bo->flags = 0;
718 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
719 bo->flags |= TEGRA_BO_BOTTOM_UP;
733 gem = drm_gem_object_lookup(file, args->handle);
735 return -ENOENT;
738 args->flags = 0;
740 if (bo->flags & TEGRA_BO_BOTTOM_UP)
741 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
820 struct tegra_drm_file *fpriv = file->driver_priv;
822 mutex_lock(&fpriv->lock);
823 idr_for_each(&fpriv->legacy_contexts, tegra_drm_context_cleanup, NULL);
825 mutex_unlock(&fpriv->lock);
827 idr_destroy(&fpriv->legacy_contexts);
828 mutex_destroy(&fpriv->lock);
835 struct drm_info_node *node = (struct drm_info_node *)s->private;
836 struct drm_device *drm = node->minor->dev;
839 mutex_lock(&drm->mode_config.fb_lock);
841 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
843 fb->base.id, fb->width, fb->height,
844 fb->format->depth,
845 fb->format->cpp[0] * 8,
849 mutex_unlock(&drm->mode_config.fb_lock);
856 struct drm_info_node *node = (struct drm_info_node *)s->private;
857 struct drm_device *drm = node->minor->dev;
858 struct tegra_drm *tegra = drm->dev_private;
861 if (tegra->domain) {
862 mutex_lock(&tegra->mm_lock);
863 drm_mm_print(&tegra->mm, &p);
864 mutex_unlock(&tegra->mm_lock);
879 minor->debugfs_root, minor);
919 client->shared_channel = host1x_channel_request(&client->base);
920 if (!client->shared_channel)
921 return -EBUSY;
923 mutex_lock(&tegra->clients_lock);
924 list_add_tail(&client->list, &tegra->clients);
925 client->drm = tegra;
926 mutex_unlock(&tegra->clients_lock);
934 mutex_lock(&tegra->clients_lock);
935 list_del_init(&client->list);
936 client->drm = NULL;
937 mutex_unlock(&tegra->clients_lock);
939 if (client->shared_channel)
940 host1x_channel_put(client->shared_channel);
947 struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
948 struct drm_device *drm = dev_get_drvdata(client->host);
949 struct tegra_drm *tegra = drm->dev_private;
954 if (client->dev->archdata.mapping) {
956 to_dma_iommu_mapping(client->dev);
957 arm_iommu_detach_device(client->dev);
960 domain = iommu_get_domain_for_dev(client->dev);
967 * domain. This allows using the IOMMU-backed DMA API.
969 if (domain && domain != tegra->domain)
972 if (tegra->domain) {
973 group = iommu_group_get(client->dev);
975 return -ENODEV;
977 if (domain != tegra->domain) {
978 err = iommu_attach_group(tegra->domain, group);
985 tegra->use_explicit_iommu = true;
988 client->group = group;
995 struct drm_device *drm = dev_get_drvdata(client->host);
996 struct tegra_drm *tegra = drm->dev_private;
999 if (client->group) {
1005 domain = iommu_get_domain_for_dev(client->dev);
1007 iommu_detach_group(tegra->domain, client->group);
1009 iommu_group_put(client->group);
1010 client->group = NULL;
1021 if (tegra->domain)
1022 size = iova_align(&tegra->carveout.domain, size);
1027 if (!tegra->domain) {
1029 * Many units only support 32-bit addresses, even on 64-bit
1030 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1032 * lower 32-bit range.
1039 return ERR_PTR(-ENOMEM);
1041 if (!tegra->domain) {
1050 alloc = alloc_iova(&tegra->carveout.domain,
1051 size >> tegra->carveout.shift,
1052 tegra->carveout.limit, true);
1054 err = -EBUSY;
1058 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1059 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1067 __free_iova(&tegra->carveout.domain, alloc);
1077 if (tegra->domain)
1078 size = iova_align(&tegra->carveout.domain, size);
1082 if (tegra->domain) {
1083 iommu_unmap(tegra->domain, dma, size);
1084 free_iova(&tegra->carveout.domain,
1085 iova_pfn(&tegra->carveout.domain, dma));
1093 struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
1102 * likely to be allocated beyond the 32-bit boundary if sufficient
1107 * 32-bit boundary.
1127 domain = iommu_get_domain_for_dev(dev->dev.parent);
1131 * 32-bit boundary, so the regular GATHER opcodes will always be
1147 drm = drm_dev_alloc(&tegra_drm_driver, &dev->dev);
1153 err = -ENOMEM;
1158 tegra->domain = iommu_domain_alloc(&platform_bus_type);
1159 if (!tegra->domain) {
1160 err = -ENOMEM;
1169 mutex_init(&tegra->clients_lock);
1170 INIT_LIST_HEAD(&tegra->clients);
1172 dev_set_drvdata(&dev->dev, drm);
1173 drm->dev_private = tegra;
1174 tegra->drm = drm;
1178 drm->mode_config.min_width = 0;
1179 drm->mode_config.min_height = 0;
1180 drm->mode_config.max_width = 0;
1181 drm->mode_config.max_height = 0;
1183 drm->mode_config.normalize_zpos = true;
1185 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
1186 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
1203 tegra->hmask = drm->mode_config.max_width - 1;
1204 tegra->vmask = drm->mode_config.max_height - 1;
1206 if (tegra->use_explicit_iommu) {
1208 u64 dma_mask = dma_get_mask(&dev->dev);
1212 start = tegra->domain->geometry.aperture_start & dma_mask;
1213 end = tegra->domain->geometry.aperture_end & dma_mask;
1216 gem_end = end - CARVEOUT_SZ;
1220 order = __ffs(tegra->domain->pgsize_bitmap);
1221 init_iova_domain(&tegra->carveout.domain, 1UL << order,
1224 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
1225 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
1227 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
1228 mutex_init(&tegra->mm_lock);
1231 DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end);
1232 DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start,
1234 } else if (tegra->domain) {
1235 iommu_domain_free(tegra->domain);
1236 tegra->domain = NULL;
1240 if (tegra->hub) {
1241 err = tegra_display_hub_prepare(tegra->hub);
1246 /* syncpoints are used for full 32-bit hardware VBLANK counters */
1247 drm->max_vblank_count = 0xffffffff;
1249 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
1272 if (tegra->hub)
1273 tegra_display_hub_cleanup(tegra->hub);
1275 if (tegra->domain) {
1276 mutex_destroy(&tegra->mm_lock);
1277 drm_mm_takedown(&tegra->mm);
1278 put_iova_domain(&tegra->carveout.domain);
1289 if (tegra->domain)
1290 iommu_domain_free(tegra->domain);
1300 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1301 struct tegra_drm *tegra = drm->dev_private;
1311 if (tegra->hub)
1312 tegra_display_hub_cleanup(tegra->hub);
1316 dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
1318 if (tegra->domain) {
1319 mutex_destroy(&tegra->mm_lock);
1320 drm_mm_takedown(&tegra->mm);
1321 put_iova_domain(&tegra->carveout.domain);
1323 iommu_domain_free(tegra->domain);
1352 { .compatible = "nvidia,tegra20-dc", },
1353 { .compatible = "nvidia,tegra20-hdmi", },
1354 { .compatible = "nvidia,tegra20-gr2d", },
1355 { .compatible = "nvidia,tegra20-gr3d", },
1356 { .compatible = "nvidia,tegra30-dc", },
1357 { .compatible = "nvidia,tegra30-hdmi", },
1358 { .compatible = "nvidia,tegra30-gr2d", },
1359 { .compatible = "nvidia,tegra30-gr3d", },
1360 { .compatible = "nvidia,tegra114-dc", },
1361 { .compatible = "nvidia,tegra114-dsi", },
1362 { .compatible = "nvidia,tegra114-hdmi", },
1363 { .compatible = "nvidia,tegra114-gr2d", },
1364 { .compatible = "nvidia,tegra114-gr3d", },
1365 { .compatible = "nvidia,tegra124-dc", },
1366 { .compatible = "nvidia,tegra124-sor", },
1367 { .compatible = "nvidia,tegra124-hdmi", },
1368 { .compatible = "nvidia,tegra124-dsi", },
1369 { .compatible = "nvidia,tegra124-vic", },
1370 { .compatible = "nvidia,tegra132-dsi", },
1371 { .compatible = "nvidia,tegra210-dc", },
1372 { .compatible = "nvidia,tegra210-dsi", },
1373 { .compatible = "nvidia,tegra210-sor", },
1374 { .compatible = "nvidia,tegra210-sor1", },
1375 { .compatible = "nvidia,tegra210-vic", },
1376 { .compatible = "nvidia,tegra210-nvdec", },
1377 { .compatible = "nvidia,tegra186-display", },
1378 { .compatible = "nvidia,tegra186-dc", },
1379 { .compatible = "nvidia,tegra186-sor", },
1380 { .compatible = "nvidia,tegra186-sor1", },
1381 { .compatible = "nvidia,tegra186-vic", },
1382 { .compatible = "nvidia,tegra186-nvdec", },
1383 { .compatible = "nvidia,tegra194-display", },
1384 { .compatible = "nvidia,tegra194-dc", },
1385 { .compatible = "nvidia,tegra194-sor", },
1386 { .compatible = "nvidia,tegra194-vic", },
1387 { .compatible = "nvidia,tegra194-nvdec", },
1388 { .compatible = "nvidia,tegra234-vic", },
1420 return -ENODEV;
1445 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");